From patchwork Sun Mar 13 00:21:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 12778990 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC206C43219 for ; Sun, 13 Mar 2022 00:22:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233175AbiCMAXM (ORCPT ); Sat, 12 Mar 2022 19:23:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233165AbiCMAXL (ORCPT ); Sat, 12 Mar 2022 19:23:11 -0500 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8B219BBB3; Sat, 12 Mar 2022 16:22:04 -0800 (PST) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id B2D16223F0; Sun, 13 Mar 2022 01:22:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1647130922; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ufBbvQAexSriWvMXZv4flnbt/7xBdIcOYOogujbLjik=; b=BfHPAMIEaeGcamQgRCUDV1J5SGSmicKbpI4sNYxpxIkrNZwm7vVO1vQV5A5WLPSezxiOrw Bq1s/hq6LzzqpGUnsmtvrwLKcErEDbhguD2ZkRW4ktiDvv+fqZI1GEK0PVv7a/AeFpdTXp 2azNCw9ev6h0qsdVojM7f1UJH5xEh7U= From: Michael Walle To: "David S . Miller" , Jakub Kicinski , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Walle Subject: [PATCH net-next 3/3] et: mdio: mscc-miim: add lan966x internal phy reset support Date: Sun, 13 Mar 2022 01:21:53 +0100 Message-Id: <20220313002153.11280-4-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220313002153.11280-1-michael@walle.cc> References: <20220313002153.11280-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The LAN966x has two internal PHYs which are in reset by default. The driver already supported the internal PHYs of the SparX-5. Now add support for the LAN966x, too. Add a new compatible to distinguish them. The LAN966x has additional control bits in this register, thus convert the regmap_write() to regmap_update_bits() to leave the remaining bits untouched. This doesn't change anything for the SparX-5 SoC, because there, the register consists only of reset bits. Signed-off-by: Michael Walle --- drivers/net/mdio/mdio-mscc-miim.c | 59 +++++++++++++++++++++---------- 1 file changed, 41 insertions(+), 18 deletions(-) diff --git a/drivers/net/mdio/mdio-mscc-miim.c b/drivers/net/mdio/mdio-mscc-miim.c index 7773d5019e66..d082a13d9af3 100644 --- a/drivers/net/mdio/mdio-mscc-miim.c +++ b/drivers/net/mdio/mdio-mscc-miim.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #define MSCC_MIIM_REG_STATUS 0x0 @@ -36,11 +37,19 @@ #define PHY_CFG_PHY_RESET (BIT(5) | BIT(6) | BIT(7) | BIT(8)) #define MSCC_PHY_REG_PHY_STATUS 0x4 +#define LAN966X_CUPHY_COMMON_CFG 0x0 +#define CUPHY_COMMON_CFG_RESET_N BIT(0) + +struct mscc_miim_info { + unsigned int phy_reset_offset; + unsigned int phy_reset_mask; +}; + struct mscc_miim_dev { struct regmap *regs; int mii_status_offset; struct regmap *phy_regs; - int phy_reset_offset; + const struct mscc_miim_info *info; }; /* When high resolution timers aren't built-in: we can't use usleep_range() as @@ -157,27 +166,29 @@ static int mscc_miim_write(struct mii_bus *bus, int mii_id, static int mscc_miim_reset(struct mii_bus *bus) { struct mscc_miim_dev *miim = bus->priv; - int offset = miim->phy_reset_offset; - int mask = PHY_CFG_PHY_ENA | PHY_CFG_PHY_COMMON_RESET | - PHY_CFG_PHY_RESET; + unsigned int offset, mask; int ret; - if (miim->phy_regs) { - ret = regmap_write(miim->phy_regs, offset, 0); - if (ret < 0) { - WARN_ONCE(1, "mscc reset set error %d\n", ret); - return ret; - } + if (!miim->phy_regs || !miim->info) + return 0; - ret = regmap_write(miim->phy_regs, offset, mask); - if (ret < 0) { - WARN_ONCE(1, "mscc reset clear error %d\n", ret); - return ret; - } + offset = miim->info->phy_reset_offset; + mask = miim->info->phy_reset_mask; + + ret = regmap_update_bits(miim->phy_regs, offset, mask, 0); + if (ret < 0) { + WARN_ONCE(1, "mscc reset set error %d\n", ret); + return ret; + } - mdelay(500); + ret = regmap_update_bits(miim->phy_regs, offset, mask, mask); + if (ret < 0) { + WARN_ONCE(1, "mscc reset clear error %d\n", ret); + return ret; } + mdelay(500); + return 0; } @@ -272,7 +283,7 @@ static int mscc_miim_probe(struct platform_device *pdev) miim = bus->priv; miim->phy_regs = phy_regmap; - miim->phy_reset_offset = MSCC_PHY_REG_PHY_CFG; + miim->info = device_get_match_data(&pdev->dev); ret = of_mdiobus_register(bus, pdev->dev.of_node); if (ret < 0) { @@ -294,8 +305,20 @@ static int mscc_miim_remove(struct platform_device *pdev) return 0; } +static const struct mscc_miim_info mscc_ocelot_miim_info = { + .phy_reset_offset = MSCC_PHY_REG_PHY_CFG, + .phy_reset_mask = PHY_CFG_PHY_ENA | PHY_CFG_PHY_COMMON_RESET | + PHY_CFG_PHY_RESET, +}; + +static const struct mscc_miim_info mscc_lan966x_miim_info = { + .phy_reset_offset = LAN966X_CUPHY_COMMON_CFG, + .phy_reset_mask = CUPHY_COMMON_CFG_RESET_N, +}; + static const struct of_device_id mscc_miim_match[] = { - { .compatible = "mscc,ocelot-miim" }, + { .compatible = "mscc,ocelot-miim", .data = &mscc_ocelot_miim_info }, + { .compatible = "mscc,lan966x-miim", .data = &mscc_lan966x_miim_info }, { } }; MODULE_DEVICE_TABLE(of, mscc_miim_match);