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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2022 12:47:20.4389 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 253bf52a-29a2-4fca-2e0e-08da04ef9d1f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2720 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org When showing the available management devices, check if VDPA_ATTR_DEV_SUPPORTED_FEATURES feature is available and print the supported features for a management device. Examples: $ vdpa mgmtdev show auxiliary/mlx5_core.sf.1: supported_classes net max_supported_vqs 257 dev_features CSUM GUEST_CSUM MTU HOST_TSO4 HOST_TSO6 STATUS CTRL_VQ MQ \ CTRL_MAC_ADDR VERSION_1 ACCESS_PLATFORM $ vdpa -jp mgmtdev show { "mgmtdev": { "auxiliary/mlx5_core.sf.1": { "supported_classes": [ "net" ], "max_supported_vqs": 257, "dev_features": [ "CSUM","GUEST_CSUM","MTU","HOST_TSO4","HOST_TSO6","STATUS","CTRL_VQ","MQ",\ "CTRL_MAC_ADDR","VERSION_1","ACCESS_PLATFORM" ] } } } Reviewed-by: Si-Wei Liu Acked-by: Jason Wang Signed-off-by: Eli Cohen --- vdpa/vdpa.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/vdpa/vdpa.c b/vdpa/vdpa.c index 1326a63e729d..c63bf52d3c49 100644 --- a/vdpa/vdpa.c +++ b/vdpa/vdpa.c @@ -84,6 +84,7 @@ static const enum mnl_attr_data_type vdpa_policy[VDPA_ATTR_MAX + 1] = { [VDPA_ATTR_DEV_MAX_VQ_SIZE] = MNL_TYPE_U16, [VDPA_ATTR_DEV_NEGOTIATED_FEATURES] = MNL_TYPE_U64, [VDPA_ATTR_DEV_MGMTDEV_MAX_VQS] = MNL_TYPE_U32, + [VDPA_ATTR_DEV_SUPPORTED_FEATURES] = MNL_TYPE_U64, }; static int attr_cb(const struct nlattr *attr, void *data) @@ -496,14 +497,14 @@ static void print_features(struct vdpa *vdpa, uint64_t features, bool mgmtdevf, static void pr_out_mgmtdev_show(struct vdpa *vdpa, const struct nlmsghdr *nlh, struct nlattr **tb) { + uint64_t classes = 0; const char *class; unsigned int i; pr_out_handle_start(vdpa, tb); if (tb[VDPA_ATTR_MGMTDEV_SUPPORTED_CLASSES]) { - uint64_t classes = mnl_attr_get_u64(tb[VDPA_ATTR_MGMTDEV_SUPPORTED_CLASSES]); - + classes = mnl_attr_get_u64(tb[VDPA_ATTR_MGMTDEV_SUPPORTED_CLASSES]); pr_out_array_start(vdpa, "supported_classes"); for (i = 1; i < 64; i++) { @@ -524,6 +525,16 @@ static void pr_out_mgmtdev_show(struct vdpa *vdpa, const struct nlmsghdr *nlh, print_uint(PRINT_ANY, "max_supported_vqs", " max_supported_vqs %d", num_vqs); } + if (tb[VDPA_ATTR_DEV_SUPPORTED_FEATURES]) { + uint64_t features; + + features = mnl_attr_get_u64(tb[VDPA_ATTR_DEV_SUPPORTED_FEATURES]); + if (classes & BIT(VIRTIO_ID_NET)) + print_features(vdpa, features, true, VIRTIO_ID_NET); + else + print_features(vdpa, features, true, 0); + } + pr_out_handle_end(vdpa); }