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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id e10-20020a056a00162a00b004f6fc39c081sm1612275pfc.211.2022.03.16.00.59.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 00:59:14 -0700 (PDT) From: Andy Chiu To: davem@davemloft.net, kuba@kernel.org, michal.simek@xilinx.com, linux@armlinux.org.uk, robert.hancock@calian.co, netdev@vger.kernel.org Cc: Andy Chiu , Greentime Hu Subject: [PATCH] net: axiemac: initialize PHY before device reset Date: Wed, 16 Mar 2022 15:57:07 +0800 Message-Id: <20220316075707.61321-1-andy.chiu@sifive.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org On some platforms, the clock of internal (Xilinx's PCS/PMA) PHY was sourced externally and was not enabled by the time the FPGA logic was loaded. Specifically, the clock was souced from an external PHY's SGMII ref clock, which would not start until the driver configured it , on vcu118. Under such condition, the core would boot up in a state where the PCS PHY could not be found on the bus. Or, even if the PCS PHY could be found, the link would be broken and A/N would not complete. To fix this, the Ethernet should be reset every time after the clock being restarted at phylink_of_phy_connect(). Since phylink_of_phy_connect() configures the external PHY base on DT only, it is safe to move it prior to the device reset. Related-to: 'd836ed73a3cb ("net: axienet: reset core on initialization prior to MDIO access")' Fixes: '1a02556086fc ("net: axienet: Properly handle PCS/PMA PHY for 1000BaseX mode")' Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu --- drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index c7eb05e4a6bf..6fd5157f0a6d 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -1141,6 +1141,12 @@ static int axienet_open(struct net_device *ndev) dev_dbg(&ndev->dev, "axienet_open()\n"); + ret = phylink_of_phy_connect(lp->phylink, lp->dev->of_node, 0); + if (ret) { + dev_err(lp->dev, "phylink_of_phy_connect() failed: %d\n", ret); + return ret; + } + /* When we do an Axi Ethernet reset, it resets the complete core * including the MDIO. MDIO must be disabled before resetting. * Hold MDIO bus lock to avoid MDIO accesses during the reset. @@ -1149,12 +1155,6 @@ static int axienet_open(struct net_device *ndev) ret = axienet_device_reset(ndev); axienet_unlock_mii(lp); - ret = phylink_of_phy_connect(lp->phylink, lp->dev->of_node, 0); - if (ret) { - dev_err(lp->dev, "phylink_of_phy_connect() failed: %d\n", ret); - return ret; - } - phylink_start(lp->phylink); /* Enable worker thread for Axi DMA error handling */