From patchwork Thu Mar 17 18:36:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maciej Fijalkowski X-Patchwork-Id: 12784463 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64249C433EF for ; Thu, 17 Mar 2022 18:37:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237472AbiCQSjD (ORCPT ); Thu, 17 Mar 2022 14:39:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237479AbiCQSjB (ORCPT ); Thu, 17 Mar 2022 14:39:01 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C80B114DDE; Thu, 17 Mar 2022 11:37:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647542263; x=1679078263; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+aM5r8r1moVYf5XPT33TV5YGB8tm7BfoYyZ/LZfWi6A=; b=K3mA1IR+WkA9j+KieCSbx2AgK3o1EDSy0RXXo0vPtPYpaRujAlcG15cd fveqqVoXIRXi1YfH9qnAW2UQSPQ0HLPa+0yo2FpH+rBomutpea2fZzYpR 6PEyFYp2cbAUNAXvpiupi3Ueml2bGoDSDDnBTOMGPtGlTozgPq1Lekm83 2DOo2qEWby7dqEWxtsrNprQSp5elXt2GI9JzM99TGMwZrlAFhuus92Up8 Rrna4Z7LcSAG5Xw3Ud0WXjp6Ca3YbOXXri3ubUa+S8EwOoZ3Zv2is5Ipa C0UwktBZdnupXQGZbbkwPeoI+Y4ePJuMOItzXMLMCKCippuwIgs/jc2iV w==; X-IronPort-AV: E=McAfee;i="6200,9189,10289"; a="244405597" X-IronPort-AV: E=Sophos;i="5.90,188,1643702400"; d="scan'208";a="244405597" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Mar 2022 11:37:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,188,1643702400"; d="scan'208";a="558057204" Received: from boxer.igk.intel.com ([10.102.20.173]) by orsmga008.jf.intel.com with ESMTP; 17 Mar 2022 11:37:40 -0700 From: Maciej Fijalkowski To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, bpf@vger.kernel.org, anthony.l.nguyen@intel.com, kuba@kernel.org, davem@davemloft.net, magnus.karlsson@intel.com, alexandr.lobakin@intel.com, Maciej Fijalkowski Subject: [PATCH intel-net 3/3] ice: clear cmd_type_offset_bsz for TX rings Date: Thu, 17 Mar 2022 19:36:29 +0100 Message-Id: <20220317183629.340350-4-maciej.fijalkowski@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220317183629.340350-1-maciej.fijalkowski@intel.com> References: <20220317183629.340350-1-maciej.fijalkowski@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Currently when XDP rings are created, each descriptor gets its DD bit set, which turns out to be the wrong approach as it can lead to a situation where more descriptors get cleaned than it was supposed to, e.g. when AF_XDP busy poll is run with a large batch size. In this situation, the driver would request for more buffers than it is able to handle. Fix this by not setting the DD bits in ice_xdp_alloc_setup_rings(). They should be initialized to zero instead. Fixes: 9610bd988df9 ("ice: optimize XDP_TX workloads") Signed-off-by: Maciej Fijalkowski Tested-by: Shwetha Nagaraju --- drivers/net/ethernet/intel/ice/ice_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c index c3c73a61bfd0..5332bb24001a 100644 --- a/drivers/net/ethernet/intel/ice/ice_main.c +++ b/drivers/net/ethernet/intel/ice/ice_main.c @@ -2533,7 +2533,7 @@ static int ice_xdp_alloc_setup_rings(struct ice_vsi *vsi) spin_lock_init(&xdp_ring->tx_lock); for (j = 0; j < xdp_ring->count; j++) { tx_desc = ICE_TX_DESC(xdp_ring, j); - tx_desc->cmd_type_offset_bsz = cpu_to_le64(ICE_TX_DESC_DTYPE_DESC_DONE); + tx_desc->cmd_type_offset_bsz = 0; } }