@@ -1669,21 +1669,17 @@ unsigned lmc_mii_readreg (lmc_softc_t * const sc, unsigned devaddr, unsigned reg
LMC_CSR_WRITE (sc, csr_9, dataval);
lmc_delay ();
- /* __SLOW_DOWN_IO; */
LMC_CSR_WRITE (sc, csr_9, dataval | 0x10000);
lmc_delay ();
- /* __SLOW_DOWN_IO; */
}
for (i = 19; i > 0; i--)
{
LMC_CSR_WRITE (sc, csr_9, 0x40000);
lmc_delay ();
- /* __SLOW_DOWN_IO; */
retval = (retval << 1) | ((LMC_CSR_READ (sc, csr_9) & 0x80000) ? 1 : 0);
LMC_CSR_WRITE (sc, csr_9, 0x40000 | 0x10000);
lmc_delay ();
- /* __SLOW_DOWN_IO; */
}
return (retval >> 1) & 0xffff;
@@ -1708,10 +1704,8 @@ void lmc_mii_writereg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno,
LMC_CSR_WRITE (sc, csr_9, datav);
lmc_delay ();
- /* __SLOW_DOWN_IO; */
LMC_CSR_WRITE (sc, csr_9, (datav | 0x10000));
lmc_delay ();
- /* __SLOW_DOWN_IO; */
i--;
}
@@ -1720,10 +1714,8 @@ void lmc_mii_writereg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno,
{
LMC_CSR_WRITE (sc, csr_9, 0x40000);
lmc_delay ();
- /* __SLOW_DOWN_IO; */
LMC_CSR_WRITE (sc, csr_9, 0x50000);
lmc_delay ();
- /* __SLOW_DOWN_IO; */
i--;
}
}
@@ -44,14 +44,6 @@ typedef struct lmc___ctl lmc_ctl_t;
#define LMC_CSR_WRITE(sc, reg, val) \
outl((val), (sc)->lmc_csrs.reg)
-//#ifdef _LINUX_DELAY_H
-// #define SLOW_DOWN_IO udelay(2);
-// #undef __SLOW_DOWN_IO
-// #define __SLOW_DOWN_IO udelay(2);
-//#endif
-
-#define DELAY(n) SLOW_DOWN_IO
-
#define lmc_delay() inl(sc->lmc_csrs.csr_9)
/* This macro sync's up with the mii so that reads and writes can take place */