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Miller" , Paolo Abeni , Eric Dumazet , Florian Fainelli , Vivien Didelot , Andrew Lunn , Vladimir Oltean , Claudiu Manoil , Alexandre Belloni , UNGLinuxDriver@microchip.com, Colin Foster Subject: [PATCH net-next 4/6] net: dsa: felix: directly call ocelot_port_{set,unset}_dsa_8021q_cpu Date: Sun, 22 May 2022 00:37:41 +0300 Message-Id: <20220521213743.2735445-5-vladimir.oltean@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220521213743.2735445-1-vladimir.oltean@nxp.com> References: <20220521213743.2735445-1-vladimir.oltean@nxp.com> X-ClientProxiedBy: AM6P193CA0079.EURP193.PROD.OUTLOOK.COM (2603:10a6:209:88::20) To VI1PR04MB5136.eurprd04.prod.outlook.com (2603:10a6:803:55::19) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 62708912-01f5-43f1-6393-08da3b722f51 X-MS-TrafficTypeDiagnostic: AM0PR04MB6275:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Uzu5ir5IHO5+dIVeVVysef5mvhXaL4YZKJpqjRmX/kbUiq+dVWqVG6lnBp/TX1s/Rv1wo+Tua5GBBESfZPUmmnf6WWSSUE05r/KNr8n1sqmgO5A8YAoeW2sxzWZ/NzXmPfO/Rsmk/uLsfLasVhOezK8oKgdyzpD60wn3NDQ0k3OSNVeG+UpvjuTsVi/45c+xIta61LlCXQtTaehmL4FJzNlAkuETbh0qT1GkQYculuP6IStw1FTndqsBRkORtkr5n6xtxj+Tuype4ZJ/EUagvxR9h8aSXfzdmH/L8YHgoJB1/SZnT5Oq5ys9yWMSBjQW8FZwDEYOrPKFBi3Bqn9FatlocQmAlZojns1DIqLNIZrjAnR9Rr6W7XCfuuXD4hiv2ZTw29JQ7MD4EZ4fgsTAUU9TLcuml6/BO8+OrGl4XWwArQmWn9DFhPOxTZuVxOOkAnIGhmeZMUbiTVb8AEBeO2xTy27WpYnHSj4GbdeXvQjEywG/TjJSfhj42T/T39DboZvzRwwVraPntNm+NAzv6Fd3iKqb4MUMc4HHw1yT9blZ96zabU44QXLuLPHeeYVG9S+D65hdGC1Njjb2RfOVQYjc7TltpZ4eHY7akfwyYoZZYWL8zdqzBg0j5cy3QdEOmnJGzMJZtjaVTYR7DwCxK7WCb+q2kdD3z8mlI0lIdCDb8G5/0pXBO34U9j/zWyV98OG2ehCkIOjA/MZRIZgEdw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI1PR04MB5136.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(4636009)(366004)(6666004)(86362001)(26005)(6512007)(6506007)(52116002)(36756003)(2906002)(6486002)(8676002)(66946007)(4326008)(66476007)(66556008)(54906003)(44832011)(83380400001)(7416002)(2616005)(186003)(508600001)(38350700002)(8936002)(38100700002)(5660300002)(316002)(6916009)(1076003);DIR:OUT;SFP:1101; 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Signed-off-by: Vladimir Oltean --- drivers/net/dsa/ocelot/felix.c | 36 ++++++++---------------------- drivers/net/ethernet/mscc/ocelot.c | 8 +++++++ 2 files changed, 17 insertions(+), 27 deletions(-) diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c index b60d6e7295e1..033f7d5cc03d 100644 --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c @@ -240,31 +240,6 @@ static int felix_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) return 0; } -/* Alternatively to using the NPI functionality, that same hardware MAC - * connected internally to the enetc or fman DSA master can be configured to - * use the software-defined tag_8021q frame format. As far as the hardware is - * concerned, it thinks it is a "dumb switch" - the queues of the CPU port - * module are now disconnected from it, but can still be accessed through - * register-based MMIO. - */ -static void felix_8021q_cpu_port_init(struct ocelot *ocelot, int port) -{ - mutex_lock(&ocelot->fwd_domain_lock); - - ocelot_port_set_dsa_8021q_cpu(ocelot, port); - - mutex_unlock(&ocelot->fwd_domain_lock); -} - -static void felix_8021q_cpu_port_deinit(struct ocelot *ocelot, int port) -{ - mutex_lock(&ocelot->fwd_domain_lock); - - ocelot_port_unset_dsa_8021q_cpu(ocelot, port); - - mutex_unlock(&ocelot->fwd_domain_lock); -} - static int felix_trap_get_cpu_port(struct dsa_switch *ds, const struct ocelot_vcap_filter *trap) { @@ -423,6 +398,13 @@ static unsigned long felix_tag_npi_get_host_fwd_mask(struct dsa_switch *ds) return BIT(ocelot->num_phys_ports); } +/* Alternatively to using the NPI functionality, that same hardware MAC + * connected internally to the enetc or fman DSA master can be configured to + * use the software-defined tag_8021q frame format. As far as the hardware is + * concerned, it thinks it is a "dumb switch" - the queues of the CPU port + * module are now disconnected from it, but can still be accessed through + * register-based MMIO. + */ static const struct felix_tag_proto_ops felix_tag_npi_proto_ops = { .setup = felix_tag_npi_setup, .teardown = felix_tag_npi_teardown, @@ -440,7 +422,7 @@ static int felix_tag_8021q_setup(struct dsa_switch *ds) return err; dsa_switch_for_each_cpu_port(cpu_dp, ds) { - felix_8021q_cpu_port_init(ocelot, cpu_dp->index); + ocelot_port_set_dsa_8021q_cpu(ocelot, cpu_dp->index); /* TODO we could support multiple CPU ports in tag_8021q mode */ break; @@ -490,7 +472,7 @@ static void felix_tag_8021q_teardown(struct dsa_switch *ds) } dsa_switch_for_each_cpu_port(cpu_dp, ds) { - felix_8021q_cpu_port_deinit(ocelot, cpu_dp->index); + ocelot_port_unset_dsa_8021q_cpu(ocelot, cpu_dp->index); /* TODO we could support multiple CPU ports in tag_8021q mode */ break; diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c index 4011a7968be5..d208d57f4894 100644 --- a/drivers/net/ethernet/mscc/ocelot.c +++ b/drivers/net/ethernet/mscc/ocelot.c @@ -2195,6 +2195,8 @@ void ocelot_port_set_dsa_8021q_cpu(struct ocelot *ocelot, int port) { u16 vid; + mutex_lock(&ocelot->fwd_domain_lock); + ocelot->ports[port]->is_dsa_8021q_cpu = true; for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) @@ -2203,6 +2205,8 @@ void ocelot_port_set_dsa_8021q_cpu(struct ocelot *ocelot, int port) ocelot_update_pgid_cpu(ocelot); ocelot_apply_bridge_fwd_mask(ocelot, true); + + mutex_unlock(&ocelot->fwd_domain_lock); } EXPORT_SYMBOL_GPL(ocelot_port_set_dsa_8021q_cpu); @@ -2210,6 +2214,8 @@ void ocelot_port_unset_dsa_8021q_cpu(struct ocelot *ocelot, int port) { u16 vid; + mutex_lock(&ocelot->fwd_domain_lock); + ocelot->ports[port]->is_dsa_8021q_cpu = false; for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) @@ -2218,6 +2224,8 @@ void ocelot_port_unset_dsa_8021q_cpu(struct ocelot *ocelot, int port) ocelot_update_pgid_cpu(ocelot); ocelot_apply_bridge_fwd_mask(ocelot, true); + + mutex_unlock(&ocelot->fwd_domain_lock); } EXPORT_SYMBOL_GPL(ocelot_port_unset_dsa_8021q_cpu);