| Message ID | 20220625120335.324697-17-mkl@pengutronix.de (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 38a71fc048955c5c9d8bd14351d0f8cbcfef4f5b |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [net-next,01/22] can: xilinx_can: add Transmitter Delay Compensation (TDC) feature support | expand |
On 25/06/2022 13:03, Marc Kleine-Budde wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > From: Conor Dooley <conor.dooley@microchip.com> > > PolarFire SoC has a pair of CAN controllers, but as they were > undocumented there were omitted from the device tree. Add them. > > Link: https://lore.kernel.org/all/20220607065459.2035746-3-conor.dooley@microchip.com > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Hey Marc, Not entirely familiar with the process here. Do I apply this patch when the rest of the series gets taken, or will this patch go through the net tree? Thanks, Conor. > --- > arch/riscv/boot/dts/microchip/mpfs.dtsi | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi > index 8c3259134194..737e0e70c432 100644 > --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi > +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi > @@ -330,6 +330,24 @@ i2c1: i2c@2010b000 { > status = "disabled"; > }; > > + can0: can@2010c000 { > + compatible = "microchip,mpfs-can"; > + reg = <0x0 0x2010c000 0x0 0x1000>; > + clocks = <&clkcfg CLK_CAN0>; > + interrupt-parent = <&plic>; > + interrupts = <56>; > + status = "disabled"; > + }; > + > + can1: can@2010d000 { > + compatible = "microchip,mpfs-can"; > + reg = <0x0 0x2010d000 0x0 0x1000>; > + clocks = <&clkcfg CLK_CAN1>; > + interrupt-parent = <&plic>; > + interrupts = <57>; > + status = "disabled"; > + }; > + > mac0: ethernet@20110000 { > compatible = "cdns,macb"; > reg = <0x0 0x20110000 0x0 0x2000>; > -- > 2.35.1 > >
On 27.06.2022 07:12:47, Conor.Dooley@microchip.com wrote: > On 25/06/2022 13:03, Marc Kleine-Budde wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > From: Conor Dooley <conor.dooley@microchip.com> > > > > PolarFire SoC has a pair of CAN controllers, but as they were > > undocumented there were omitted from the device tree. Add them. > > > > Link: https://lore.kernel.org/all/20220607065459.2035746-3-conor.dooley@microchip.com > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> > > Hey Marc, > Not entirely familiar with the process here. > Do I apply this patch when the rest of the series gets taken, > or will this patch go through the net tree? Both patches: | 38a71fc04895 riscv: dts: microchip: add mpfs's CAN controllers | c878d518d7b6 dt-bindings: can: mpfs: document the mpfs CAN controller are on they way to mainline via the net-next tree. No further actions needed on your side. regards, Marc
On 27/06/2022 08:30, Marc Kleine-Budde wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > On 27.06.2022 07:12:47, Conor.Dooley@microchip.com wrote: >> On 25/06/2022 13:03, Marc Kleine-Budde wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >>> From: Conor Dooley <conor.dooley@microchip.com> >>> >>> PolarFire SoC has a pair of CAN controllers, but as they were >>> undocumented there were omitted from the device tree. Add them. >>> >>> Link: https://lore.kernel.org/all/20220607065459.2035746-3-conor.dooley@microchip.com >>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >>> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> >> >> Hey Marc, >> Not entirely familiar with the process here. >> Do I apply this patch when the rest of the series gets taken, >> or will this patch go through the net tree? > > Both patches: > > 38a71fc04895 riscv: dts: microchip: add mpfs's CAN controllers > c878d518d7b6 dt-bindings: can: mpfs: document the mpfs CAN controller > > are on they way to mainline via the net-next tree. No further actions > needed on your side. dts through the netdev tree rater than via the arch? Seems a little odd, but it'd be via my tree anyway and I don't mind & unless Palmer objects: Acked-by: Conor Dooley <conor.dooley@microchip.com>
On 27.06.2022 11:17:39, Conor.Dooley@microchip.com wrote: > On 27/06/2022 08:30, Marc Kleine-Budde wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 27.06.2022 07:12:47, Conor.Dooley@microchip.com wrote: > >> On 25/06/2022 13:03, Marc Kleine-Budde wrote: > >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > >>> > >>> From: Conor Dooley <conor.dooley@microchip.com> > >>> > >>> PolarFire SoC has a pair of CAN controllers, but as they were > >>> undocumented there were omitted from the device tree. Add them. > >>> > >>> Link: https://lore.kernel.org/all/20220607065459.2035746-3-conor.dooley@microchip.com > >>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > >>> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> > >> > >> Hey Marc, > >> Not entirely familiar with the process here. > >> Do I apply this patch when the rest of the series gets taken, > >> or will this patch go through the net tree? > > > > Both patches: > > > > 38a71fc04895 riscv: dts: microchip: add mpfs's CAN controllers > > c878d518d7b6 dt-bindings: can: mpfs: document the mpfs CAN controller > > > > are on they way to mainline via the net-next tree. No further actions > > needed on your side. > > dts through the netdev tree rater than via the arch? Seems a little odd, > but it'd be via my tree anyway and I don't mind & unless Palmer objects: > Acked-by: Conor Dooley <conor.dooley@microchip.com> It was just applied to net-next/master. Drop me a note if something should be reverted. regards, Marc
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 8c3259134194..737e0e70c432 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -330,6 +330,24 @@ i2c1: i2c@2010b000 { status = "disabled"; }; + can0: can@2010c000 { + compatible = "microchip,mpfs-can"; + reg = <0x0 0x2010c000 0x0 0x1000>; + clocks = <&clkcfg CLK_CAN0>; + interrupt-parent = <&plic>; + interrupts = <56>; + status = "disabled"; + }; + + can1: can@2010d000 { + compatible = "microchip,mpfs-can"; + reg = <0x0 0x2010d000 0x0 0x1000>; + clocks = <&clkcfg CLK_CAN1>; + interrupt-parent = <&plic>; + interrupts = <57>; + status = "disabled"; + }; + mac0: ethernet@20110000 { compatible = "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>;