| Message ID | 20220715215954.1449214-13-sean.anderson@seco.com (mailing list archive) |
|---|---|
| State | RFC |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: dpaa: Convert to phylink | expand |
On Fri, Jul 15, 2022 at 05:59:19PM -0400, Sean Anderson wrote: > This adds support for the AQR115 (which I have on my LS1046A RDB). I had a > quick look over the registers, and it seems to be compatible with the > AQR107. I couldn't find this oui anywhere, but that's what I have on my > board. It's possible that NXP used a substitute here; I can't confirm > the part number since there is a heatsink on top of the phy. If i remember correctly, the OUI can be part of the provisioning for Aquantia PHYs. And i think there is often per board provisioning, specially for the SERDEs configuration. So aQuantia/Marvell probably set this OUI, but maybe at NXP request. Did you get the part number from the schematic? That should be enough to confirm it is a AQR115. > To avoid breaking <10G ethernet on the LS1046ARDB, we must add this > vendor id as an exception to dpaa_phy_init. This will be removed once > the DPAA driver is converted to phylink. I suggest you split this into two. The PHY changes can be merged right away, and is independent of the DPAA. Given the size of this patchset, the more you can split it up into parallel submissions the better. So please submit the PHY patches independent of the rest. > Signed-off-by: Sean Anderson <sean.anderson@seco.com> For the aquantia_main.c change only: Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
On 7/16/22 2:17 PM, Andrew Lunn wrote: > On Fri, Jul 15, 2022 at 05:59:19PM -0400, Sean Anderson wrote: >> This adds support for the AQR115 (which I have on my LS1046A RDB). I had a >> quick look over the registers, and it seems to be compatible with the >> AQR107. I couldn't find this oui anywhere, but that's what I have on my >> board. It's possible that NXP used a substitute here; I can't confirm >> the part number since there is a heatsink on top of the phy. > > If i remember correctly, the OUI can be part of the provisioning for > Aquantia PHYs. And i think there is often per board provisioning, > specially for the SERDEs configuration. So aQuantia/Marvell probably > set this OUI, but maybe at NXP request. Ah, interesting. > Did you get the part number from the schematic? That should be enough > to confirm it is a AQR115. Yes, I got it off the schematic. >> To avoid breaking <10G ethernet on the LS1046ARDB, we must add this >> vendor id as an exception to dpaa_phy_init. This will be removed once >> the DPAA driver is converted to phylink. > > I suggest you split this into two. The PHY changes can be merged right > away, and is independent of the DPAA. The DPAA changes must be merged before the phy changes. At the moment, sub-10G ethernet still works on the LS1046ARDB. This is because even though we program an advertisement of only 10G link modes, the phy by default ignores the programmed advertisement. But by adding a driver for this phy, the 10G-only advertisement will take effect and no link will be established. So the DPAA change must come before the phy change. Since there is no harm, I will split the DPAA change into its own patch and place it before this one. > Given the size of this patchset, > the more you can split it up into parallel submissions the better. So > please submit the PHY patches independent of the rest. Yes, that is the strategy outlined in the cover letter. >> Signed-off-by: Sean Anderson <sean.anderson@seco.com> > > For the aquantia_main.c change only: > > Reviewed-by: Andrew Lunn <andrew@lunn.ch> > > Andrew > --Sean
diff --git a/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c b/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c index 45634579adb6..a770bab4d1ed 100644 --- a/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c +++ b/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c @@ -2886,6 +2886,7 @@ static void dpaa_adjust_link(struct net_device *net_dev) /* The Aquantia PHYs are capable of performing rate adaptation */ #define PHY_VEND_AQUANTIA 0x03a1b400 +#define PHY_VEND_AQUANTIA2 0x31c31c00 static int dpaa_phy_init(struct net_device *net_dev) { @@ -2893,6 +2894,7 @@ static int dpaa_phy_init(struct net_device *net_dev) struct mac_device *mac_dev; struct phy_device *phy_dev; struct dpaa_priv *priv; + u32 phy_vendor; priv = netdev_priv(net_dev); mac_dev = priv->mac_dev; @@ -2905,9 +2907,11 @@ static int dpaa_phy_init(struct net_device *net_dev) return -ENODEV; } + phy_vendor = phy_dev->drv->phy_id & GENMASK(31, 10); /* Unless the PHY is capable of rate adaptation */ if (mac_dev->phy_if != PHY_INTERFACE_MODE_XGMII || - ((phy_dev->drv->phy_id & GENMASK(31, 10)) != PHY_VEND_AQUANTIA)) { + (phy_vendor != PHY_VEND_AQUANTIA && + phy_vendor != PHY_VEND_AQUANTIA2)) { /* remove any features not supported by the controller */ ethtool_convert_legacy_u32_to_link_mode(mask, mac_dev->if_support); diff --git a/drivers/net/phy/aquantia_main.c b/drivers/net/phy/aquantia_main.c index 8b7a46db30e0..f9e2d20d0ec5 100644 --- a/drivers/net/phy/aquantia_main.c +++ b/drivers/net/phy/aquantia_main.c @@ -21,6 +21,7 @@ #define PHY_ID_AQR106 0x03a1b4d0 #define PHY_ID_AQR107 0x03a1b4e0 #define PHY_ID_AQCS109 0x03a1b5c2 +#define PHY_ID_AQR115 0x31c31c12 #define PHY_ID_AQR405 0x03a1b4b0 #define PHY_ID_AQR113C 0x31c31c12 @@ -672,6 +673,24 @@ static struct phy_driver aqr_driver[] = { .get_stats = aqr107_get_stats, .link_change_notify = aqr107_link_change_notify, }, +{ + PHY_ID_MATCH_MODEL(PHY_ID_AQR115), + .name = "Aquantia AQR115", + .probe = aqr107_probe, + .config_init = aqr107_config_init, + .config_aneg = aqr_config_aneg, + .config_intr = aqr_config_intr, + .handle_interrupt = aqr_handle_interrupt, + .read_status = aqr107_read_status, + .get_tunable = aqr107_get_tunable, + .set_tunable = aqr107_set_tunable, + .suspend = aqr107_suspend, + .resume = aqr107_resume, + .get_sset_count = aqr107_get_sset_count, + .get_strings = aqr107_get_strings, + .get_stats = aqr107_get_stats, + .link_change_notify = aqr107_link_change_notify, +}, { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), .name = "Aquantia AQCS109", @@ -726,6 +745,7 @@ static struct mdio_device_id __maybe_unused aqr_tbl[] = { { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR115) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
This adds support for the AQR115 (which I have on my LS1046A RDB). I had a quick look over the registers, and it seems to be compatible with the AQR107. I couldn't find this oui anywhere, but that's what I have on my board. It's possible that NXP used a substitute here; I can't confirm the part number since there is a heatsink on top of the phy. To avoid breaking <10G ethernet on the LS1046ARDB, we must add this vendor id as an exception to dpaa_phy_init. This will be removed once the DPAA driver is converted to phylink. Signed-off-by: Sean Anderson <sean.anderson@seco.com> --- Changes in v3: - New .../net/ethernet/freescale/dpaa/dpaa_eth.c | 6 +++++- drivers/net/phy/aquantia_main.c | 20 +++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-)