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Miller" , Eric Dumazet , Paolo Abeni , , Saeed Mahameed , Gal Pressman , Tariq Toukan Subject: [PATCH net-next V3 3/6] net/mlx5e: kTLS, Introduce TLS-specific create TIS Date: Wed, 27 Jul 2022 12:43:43 +0300 Message-ID: <20220727094346.10540-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220727094346.10540-1-tariqt@nvidia.com> References: <20220727094346.10540-1-tariqt@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 954c42cd-b9b7-4a52-5a66-08da6fb49231 X-MS-TrafficTypeDiagnostic: MN2PR12MB3407:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UcnEWfLR2bjRfj0pJ1OGPywAz0OBtGcHm/aokuwdxiIyY9wp2s7OjkACH4aiV7FfrVElgEw1Wx8+DSabRaNerly/8gGuGsAAvEeIaC08z3+F3Y/pJyxLJYz8k5lasDkjPiRnHSlrMYktIzX0i6ehvLeEU7msiveGPWj3H0YCY+dv3aLEWnez4AZRDq7wPUl81hVMsJWFX67+LQSE2/d+u4fd/I0CZTD+3ciDDhIeSSA+7wHq5GSV8wnwVinTHHuBWxSHlVXEcNRQmWHolBFwCdiLoLOTGid7Q7eIgVAghdpMdlhbiuL0xdGXe88bxC+UCimr8tvCiH6q5rVOwy5/HHqYPsNrHvgOUHMUzscQm8qHni50q5t9DFW0EEanbO2EKjYXSM63fegiMThBzGft0NHykb7UaLwvcVXJWckJAudPIH9mXQV1e2+9Zs2Qd99RrADgunQ97ApTJItVGKKFw4JzLE9g54OsIwBHBeiiPSitJHxlIL223tB7WOASnG/QV7xv0Y5dVcZqoxOoOcUC3NXf/M/NyRnxIvi9rxqehoCwVfxhi7qB4RouNU+OFMr531KnKXbOajUgE1Z8D3UgtpYkIu4g3DrTSizQJEBz4LqtO31+oRlMV5XOcGG2PaBAnVqo+z7FkUdB4OTGLzwOcwg9fgjfxx0GK724urce+razAr0exS9vYjMfW4Vrrnweb4EkgbHINlXEIN8+vHd2W2qEucu1I8TR6p4/n11ooOZJOoMvwOGZAoZ3YQqX6nXZGUOwmE0KWMZPs1PlOUMvO19phdvyC2kvaUW8JdBihXHGyyxF9rWS+AcfS2b4OP3iOGzky1ZZRVYsIaK3EGM/og== X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(376002)(346002)(136003)(39860400002)(396003)(46966006)(36840700001)(40470700004)(36756003)(110136005)(6666004)(41300700001)(186003)(2906002)(1076003)(7696005)(47076005)(4326008)(86362001)(316002)(107886003)(426003)(83380400001)(82310400005)(336012)(2616005)(40460700003)(356005)(5660300002)(26005)(40480700001)(8936002)(82740400003)(36860700001)(54906003)(81166007)(70586007)(8676002)(478600001)(70206006)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jul 2022 09:44:16.1975 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 954c42cd-b9b7-4a52-5a66-08da6fb49231 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3407 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org TLS TIS objects have a defined role in mapping and reaching the HW TLS contexts. Some standard TIS attributes (like LAG port affinity) are not relevant for them. Use a dedicated TLS TIS create function instead of the generic mlx5e_create_tis. Signed-off-by: Tariq Toukan Reviewed-by: Gal Pressman Signed-off-by: Saeed Mahameed --- .../ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c index fba21edf88d8..73ba2501e441 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c @@ -39,16 +39,20 @@ u16 mlx5e_ktls_get_stop_room(struct mlx5_core_dev *mdev, struct mlx5e_params *pa return stop_room; } +static void mlx5e_ktls_set_tisc(struct mlx5_core_dev *mdev, void *tisc) +{ + MLX5_SET(tisc, tisc, tls_en, 1); + MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn); + MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn); +} + static int mlx5e_ktls_create_tis(struct mlx5_core_dev *mdev, u32 *tisn) { u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; - void *tisc; - - tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); - MLX5_SET(tisc, tisc, tls_en, 1); + mlx5e_ktls_set_tisc(mdev, MLX5_ADDR_OF(create_tis_in, in, ctx)); - return mlx5e_create_tis(mdev, in, tisn); + return mlx5_core_create_tis(mdev, in, tisn); } struct mlx5e_ktls_offload_context_tx {