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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Vivien Didelot , Andrew Lunn , Vladimir Oltean , Claudiu Manoil , Alexandre Belloni , UNGLinuxDriver@microchip.com, Colin Foster , Roopa Prabhu , Nikolay Aleksandrov Subject: [PATCH v3 net-next 8/9] net: mscc: ocelot: set up tag_8021q CPU ports independent of user port affinity Date: Fri, 19 Aug 2022 20:48:19 +0300 Message-Id: <20220819174820.3585002-9-vladimir.oltean@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220819174820.3585002-1-vladimir.oltean@nxp.com> References: <20220819174820.3585002-1-vladimir.oltean@nxp.com> X-ClientProxiedBy: AM4PR0501CA0044.eurprd05.prod.outlook.com (2603:10a6:200:68::12) To VI1PR04MB5136.eurprd04.prod.outlook.com (2603:10a6:803:55::19) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a61a9ae1-20c9-495b-b6ff-08da820b0da7 X-MS-TrafficTypeDiagnostic: DU2PR04MB8551:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QweDGFG6xylO87RJ2SINw0HE7ZJEICNxbw+R1ZALYENgEFI6OIuisb1WfiAfNL7Oq0IzC5A793HxgKg32boHf3vPDqc9Qee7ljZqGvgQfQpk364hEPPDi6Zar558Lb4IXhQZlvbNxrN/+7aJvUr3asqcHxEpjhPaTE3bVyrEXdDzGqHHqvZQMvAcieK6MBMrhuOIta7Py9o0JzSOfMasQ1AcfBzuRadGUnz2joAybrt/z37spAaL8EH17QeHjSaUV4Z00KVNgPZOPWX9X9q+UYrrcfbQwSO5iC9yr2JNH5UMNA7vMLPq51vruj1lJasirB6K1C1G+XczvHa0z1k4KijfPfp/jxSO1zfYDOwTUMgBYuWV4Xz9KHiVueOcnEcKXtms2PCHq1TLvdyXLN9JoQjRGNBoTZOD6UNmaRKxZi0GflkeQo2dFrbp6AOLzfxyzghHQ9DwRlDO0Hj4bHy/gwpNjJu0CsaLgqCcGHyT2zVIbo/djHyKPf+nO3pmuvz22+4c8jwbTJH4wO7jxr5SaZNRBzqWejtbUEKboIKfyUfmTP0pIyNyhXiMMMDtfHWXbCsQ5C8a0vhFQcwarfgAJOgd99pUkEZafmHEOxSURuOZUO/6yHqlfo7tvNtcR+EPTpnAFpJ5j2b0ckpYOK94Mp/jyQ9MoOvuvmb7sZvxzl2hoXoSgh4qFVLiryVdACUyrPGnogX8dgO1LXg3PlBTjywveLSJiSBcfvaHkjIuw5cNEYYTPdSI0qjrnHfuhwQI7MevNin3GgG/VgYVs6xVrI+XVTGOnA51NF0D/tFBRY+LttH/hcEbIoDfuLxUaLiLv0imz4e+bb0mNIxEqixia0YR103hMBQs2sdDfcsXbubx8NPJbjGpDHildDGfUJlcM11Orn480nBc+yU9Kgnbqt6I/eE3qWV3d/zFmQEq+Akfp0bvt1UICzCNlKWKen6iTV4ZPk3IA7jsFtrknDb3X3R/EI2rO6HGvvtXq3D7qinseZLxGxtuAU19mBd8FogrFvAYh4eLgBzIDRhRSjfsbvyQ+Gt7aoecmfyHvCbrkUozhZfKJGoNF9F87Uuvdco2xRd81Y5FQ8RsAnlDCeEhkHruX8NTmvWKoWQu/CdKz0FpuPzD/OhEX6Z7JfpkmGcq9sfGZgsPoXFK85Y3L+XzuHHWogRoTFiWWZj8rF7FWFTaIAKB2ZvIleYUSbzVThg00kN2khOWSSLMc7Oj4ezQukLBCllKEg+xN0bRCJ+hrqmSof0Q5rddcJOcSzmGLG6zr4X9w/r2s0zivYB4JfcMPS0yvwl9naFLB174+dfciukHaZWWfXMpvI4llOn0I4Y5WrhqruCxgFkZH1tcQiizFwniIiYgRMU//YS2IVab6hvBFyC0f1t46+acld/gMrKdZnA+jHse2b/Hz7+5OPpVCjy3i5wOBU9U6oRU/vk5W2r1xENC/wMhUEh8Ncpz0PNeoItjNaK+lFM5tHhMillHWUcMlmM3lJLKnPyQ35vgj/hfHBSjTGlDhtAoDz/9xG1SxZD8nkEWgKkfOQgeqYNSOPiw7NeMjTZSpRPguQ37uQTUfNu20Zgu8VXbNTcNkdJ9D0POyUR4gm9aSd9N0DA98g== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a61a9ae1-20c9-495b-b6ff-08da820b0da7 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5136.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2022 17:48:41.3255 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: STaJqneH9zWr40a/z2UvYT0NJgzMydUb2RbCp5ZGEzW7COmdQNlIhGcuy7Xb8MhOyIvDCiLy6129SNBUka9NOg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8551 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org This is a partial revert of commit c295f9831f1d ("net: mscc: ocelot: switch from {,un}set to {,un}assign for tag_8021q CPU ports"), because as it turns out, this isn't how tag_8021q CPU ports under a LAG are supposed to work. Under that scenario, all user ports are "assigned" to the single tag_8021q CPU port represented by the logical port corresponding to the bonding interface. So one CPU port in a LAG would have is_dsa_8021q_cpu set to true (the one whose physical port ID is equal to the logical port ID), and the other one to false. In turn, this makes 2 undesirable things happen: (1) PGID_CPU contains only the first physical CPU port, rather than both (2) only the first CPU port will be added to the private VLANs used by ocelot for VLAN-unaware bridging To make the driver behave in the same way for both bonded CPU ports, we need to bring back the old concept of setting up a port as a tag_8021q CPU port, and this is what deals with VLAN membership and PGID_CPU updating. But we also need the CPU port "assignment" (the user to CPU port affinity), and this is what updates the PGID_SRC forwarding rules. All DSA CPU ports are statically configured for tag_8021q mode when the tagging protocol is changed to ocelot-8021q. User ports are "assigned" to one CPU port or the other dynamically (this will be handled by a future change). Signed-off-by: Vladimir Oltean --- v1->v2: patch is new v2->v3: export the ocelot_port_teardown_dsa_8021q_cpu() symbol drivers/net/dsa/ocelot/felix.c | 6 +++ drivers/net/ethernet/mscc/ocelot.c | 64 +++++++++++++++--------------- include/soc/mscc/ocelot.h | 2 + 3 files changed, 40 insertions(+), 32 deletions(-) diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c index aadb0bd7c24f..ee19ed96f284 100644 --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c @@ -445,6 +445,9 @@ static int felix_tag_8021q_setup(struct dsa_switch *ds) if (err) return err; + dsa_switch_for_each_cpu_port(dp, ds) + ocelot_port_setup_dsa_8021q_cpu(ocelot, dp->index); + dsa_switch_for_each_user_port(dp, ds) ocelot_port_assign_dsa_8021q_cpu(ocelot, dp->index, dp->cpu_dp->index); @@ -493,6 +496,9 @@ static void felix_tag_8021q_teardown(struct dsa_switch *ds) dsa_switch_for_each_user_port(dp, ds) ocelot_port_unassign_dsa_8021q_cpu(ocelot, dp->index); + dsa_switch_for_each_cpu_port(dp, ds) + ocelot_port_teardown_dsa_8021q_cpu(ocelot, dp->index); + dsa_tag_8021q_unregister(ds); } diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c index d4649e4ee0e7..8468f0d4aa88 100644 --- a/drivers/net/ethernet/mscc/ocelot.c +++ b/drivers/net/ethernet/mscc/ocelot.c @@ -2196,61 +2196,61 @@ static void ocelot_update_pgid_cpu(struct ocelot *ocelot) ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU); } -void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, - int cpu) +void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu) { struct ocelot_port *cpu_port = ocelot->ports[cpu]; u16 vid; mutex_lock(&ocelot->fwd_domain_lock); - ocelot->ports[port]->dsa_8021q_cpu = cpu_port; + cpu_port->is_dsa_8021q_cpu = true; - if (!cpu_port->is_dsa_8021q_cpu) { - cpu_port->is_dsa_8021q_cpu = true; + for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) + ocelot_vlan_member_add(ocelot, cpu, vid, true); - for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) - ocelot_vlan_member_add(ocelot, cpu, vid, true); - - ocelot_update_pgid_cpu(ocelot); - } - - ocelot_apply_bridge_fwd_mask(ocelot, true); + ocelot_update_pgid_cpu(ocelot); mutex_unlock(&ocelot->fwd_domain_lock); } -EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu); +EXPORT_SYMBOL_GPL(ocelot_port_setup_dsa_8021q_cpu); -void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port) +void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu) { - struct ocelot_port *cpu_port = ocelot->ports[port]->dsa_8021q_cpu; - bool keep = false; + struct ocelot_port *cpu_port = ocelot->ports[cpu]; u16 vid; - int p; mutex_lock(&ocelot->fwd_domain_lock); - ocelot->ports[port]->dsa_8021q_cpu = NULL; + cpu_port->is_dsa_8021q_cpu = false; - for (p = 0; p < ocelot->num_phys_ports; p++) { - if (!ocelot->ports[p]) - continue; + for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) + ocelot_vlan_member_del(ocelot, cpu_port->index, vid); - if (ocelot->ports[p]->dsa_8021q_cpu == cpu_port) { - keep = true; - break; - } - } + ocelot_update_pgid_cpu(ocelot); - if (!keep) { - cpu_port->is_dsa_8021q_cpu = false; + mutex_unlock(&ocelot->fwd_domain_lock); +} +EXPORT_SYMBOL_GPL(ocelot_port_teardown_dsa_8021q_cpu); - for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) - ocelot_vlan_member_del(ocelot, cpu_port->index, vid); +void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, + int cpu) +{ + struct ocelot_port *cpu_port = ocelot->ports[cpu]; - ocelot_update_pgid_cpu(ocelot); - } + mutex_lock(&ocelot->fwd_domain_lock); + ocelot->ports[port]->dsa_8021q_cpu = cpu_port; + ocelot_apply_bridge_fwd_mask(ocelot, true); + + mutex_unlock(&ocelot->fwd_domain_lock); +} +EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu); + +void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port) +{ + mutex_lock(&ocelot->fwd_domain_lock); + + ocelot->ports[port]->dsa_8021q_cpu = NULL; ocelot_apply_bridge_fwd_mask(ocelot, true); mutex_unlock(&ocelot->fwd_domain_lock); diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index ac151ecc7f19..4c8818576437 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -875,6 +875,8 @@ void ocelot_deinit(struct ocelot *ocelot); void ocelot_init_port(struct ocelot *ocelot, int port); void ocelot_deinit_port(struct ocelot *ocelot, int port); +void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu); +void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu); void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, int cpu); void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port); u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port);