Message ID | 20220912104634.302264-1-biju.das.jz@bp.renesas.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Netdev Maintainers |
Headers | show |
Series | [net-next] ravb: Add RZ/G2L MII interface support | expand |
Hi All, > Subject: [PATCH net-next] ravb: Add RZ/G2L MII interface support > > EMAC IP found on RZ/G2L Gb ethernet supports MII interface. > This patch adds support for selecting MII interface mode. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > drivers/net/ethernet/renesas/ravb.h | 5 +++++ > drivers/net/ethernet/renesas/ravb_main.c | 8 +++++++- > 2 files changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/renesas/ravb.h > b/drivers/net/ethernet/renesas/ravb.h > index b980bce763d3..c5ef43f06ea3 100644 > --- a/drivers/net/ethernet/renesas/ravb.h > +++ b/drivers/net/ethernet/renesas/ravb.h > @@ -189,6 +189,7 @@ enum ravb_reg { > PSR = 0x0528, > PIPR = 0x052c, > CXR31 = 0x0530, /* RZ/G2L only */ > + CXR35 = 0x0540, /* RZ/G2L only */ Oops. I have sent v2 replacing spaces with tab. Cheers, Biju > MPR = 0x0558, > PFTCR = 0x055c, > PFRCR = 0x0560, > @@ -965,6 +966,10 @@ enum CXR31_BIT { > CXR31_SEL_LINK1 = 0x00000008, > }; > > +enum CXR35_BIT { > + CXR35_SEL_MII = 0x03E80002, > +}; > + > enum CSR0_BIT { > CSR0_TPE = 0x00000010, > CSR0_RPE = 0x00000020, > diff --git a/drivers/net/ethernet/renesas/ravb_main.c > b/drivers/net/ethernet/renesas/ravb_main.c > index b357ac4c56c5..6f6bf11995b0 100644 > --- a/drivers/net/ethernet/renesas/ravb_main.c > +++ b/drivers/net/ethernet/renesas/ravb_main.c > @@ -540,7 +540,13 @@ static void ravb_emac_init_gbeth(struct net_device > *ndev) > /* E-MAC interrupt enable register */ > ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); > > - ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, > CXR31_SEL_LINK0); > + if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { > + ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, > 0); > + ravb_write(ndev, CXR35_SEL_MII, CXR35); > + } else { > + ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, > + CXR31_SEL_LINK0); > + } > } > > static void ravb_emac_init_rcar(struct net_device *ndev) > -- > 2.25.1
diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index b980bce763d3..c5ef43f06ea3 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -189,6 +189,7 @@ enum ravb_reg { PSR = 0x0528, PIPR = 0x052c, CXR31 = 0x0530, /* RZ/G2L only */ + CXR35 = 0x0540, /* RZ/G2L only */ MPR = 0x0558, PFTCR = 0x055c, PFRCR = 0x0560, @@ -965,6 +966,10 @@ enum CXR31_BIT { CXR31_SEL_LINK1 = 0x00000008, }; +enum CXR35_BIT { + CXR35_SEL_MII = 0x03E80002, +}; + enum CSR0_BIT { CSR0_TPE = 0x00000010, CSR0_RPE = 0x00000020, diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index b357ac4c56c5..6f6bf11995b0 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -540,7 +540,13 @@ static void ravb_emac_init_gbeth(struct net_device *ndev) /* E-MAC interrupt enable register */ ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); - ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, CXR31_SEL_LINK0); + if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { + ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); + ravb_write(ndev, CXR35_SEL_MII, CXR35); + } else { + ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, + CXR31_SEL_LINK0); + } } static void ravb_emac_init_rcar(struct net_device *ndev)
EMAC IP found on RZ/G2L Gb ethernet supports MII interface. This patch adds support for selecting MII interface mode. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/net/ethernet/renesas/ravb.h | 5 +++++ drivers/net/ethernet/renesas/ravb_main.c | 8 +++++++- 2 files changed, 12 insertions(+), 1 deletion(-)