| Message ID | 20220927195842.44641-2-gerhard@engleder-embedded.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | ff46c610abd62a3dc120dc05ad726b2a47d347ea |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | tsnep: multi queue support and some other improvements | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Clearly marked for net-next |
| netdev/fixes_present | success | Fixes tag not required for -next series |
| netdev/subject_prefix | success | Link |
| netdev/cover_letter | success | Series has a cover letter |
| netdev/patch_count | success | Link |
| netdev/header_inline | success | No static functions without inline keyword in header files |
| netdev/build_32bit | success | Errors and warnings before: 0 this patch: 0 |
| netdev/cc_maintainers | success | CCed 9 of 9 maintainers |
| netdev/build_clang | success | Errors and warnings before: 0 this patch: 0 |
| netdev/module_param | success | Was 0 now: 0 |
| netdev/verify_signedoff | success | Signed-off-by tag matches author and committer |
| netdev/check_selftest | success | No net selftest shell script |
| netdev/verify_fixes | success | No Fixes tag |
| netdev/build_allmodconfig_warn | success | Errors and warnings before: 0 this patch: 0 |
| netdev/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 8 lines checked |
| netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| netdev/source_inline | success | Was 0 now: 0 |
On Tue, 27 Sep 2022 21:58:37 +0200, Gerhard Engleder wrote: > Within SoCs like ZynqMP, FPGA logic can be connected to different kinds > of AXI master ports. Also cache coherent AXI master ports are available. > The property "dma-coherent" is used to signal that DMA is cache > coherent. > > Add "dma-coherent" property to allow the configuration of cache coherent > DMA. > > Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com> > --- > Documentation/devicetree/bindings/net/engleder,tsnep.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml index d0e1476e15b5..37e08ee744a8 100644 --- a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml +++ b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml @@ -22,6 +22,8 @@ properties: interrupts: maxItems: 1 + dma-coherent: true + local-mac-address: true mac-address: true
Within SoCs like ZynqMP, FPGA logic can be connected to different kinds of AXI master ports. Also cache coherent AXI master ports are available. The property "dma-coherent" is used to signal that DMA is cache coherent. Add "dma-coherent" property to allow the configuration of cache coherent DMA. Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com> --- Documentation/devicetree/bindings/net/engleder,tsnep.yaml | 2 ++ 1 file changed, 2 insertions(+)