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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Jan Petrous , Andrew Lunn Cc: Chester Lin , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger Subject: [PATCH v2 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver Date: Mon, 28 Nov 2022 13:49:17 +0800 Message-Id: <20221128054920.2113-3-clin@suse.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221128054920.2113-1-clin@suse.com> References: <20221128054920.2113-1-clin@suse.com> X-ClientProxiedBy: TYCP286CA0146.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:31b::11) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0402MB3439:EE_|AS8PR04MB7655:EE_ X-MS-Office365-Filtering-Correlation-Id: f3a04ac4-c047-4de7-c834-08dad1045da8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7t1WENTYLKuiITAQ9eRCK/TpAZbqmFZgbyqFP0bYOmHIoW3/Sa3hyPIT9DD/T8OYKyMIvWFt31GOv2j/YZjgw4GfhL+4LYxLFIGPqOkuOsMNe+HSH2UiXkUPzH22VA/RUqyPRPuPwb8Vf0zAW8qwop0VRC6+KVNsfDmp1KpkCPvMo8H9nd5Pb67eddTpNfBxgoQ07vvQnvBnmmUUh7mH1gvY8yVLD7Gj02hHg43WeDa0g/IVna4fiBvrScDB5x63UJvdjg+Ha6jeLB+JE/1hRflHkMx2/cpArjoDnLcjx5Jemiun3+6KIK6FIhguHzbarouEsYi9IZ6WKq00ozS757NjiVGDCUkWB6ndzf7aGk22oeGDvNfFtPjivJIFyly/3iEGtlNmOGf3b0czvsn49KJNM4K+1+LiO202NSO6XqxjGsZzIG2CEYjqx0fCyFyr5C0rOnRhxH4nmwzZtYL7vQY3KxMaHcav0876hkYMoAuj1l9ow+RvIn7EkDcoYoS1tfOo2c3sUXMU1OFm+5V/+dvEmyY1qawEUaImmHsLLgBemyb89qqgWbbfnWQUL4+YCKAsgZQf10Qu+mNFfZit1ywuQmXBn9hdlBVRY1+u66AZggBa4/G03i4LqCqgmI39d+p4pkiwofm8wVJR5jbQ4PAwXDpMOl2no+rZ7OXOOXY= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI1PR0402MB3439.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(39860400002)(366004)(346002)(136003)(396003)(376002)(451199015)(2616005)(6506007)(6512007)(36756003)(7416002)(1076003)(186003)(5660300002)(54906003)(86362001)(110136005)(66476007)(8676002)(4326008)(66946007)(66556008)(2906002)(41300700001)(38100700002)(316002)(83380400001)(8936002)(478600001)(6486002)(107886003)(6666004);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VLRxUtXycK94x6kM77Uwc3bkUS3kyXPSqtIQDGFzYUEeQJLUUEbIGNBWYKIPVHxJKiSeY28lzGoIlAx4ISRMJF08Jf+SVO3N67kSwOH3vmN/eTOdc5+wRYl4iaiHLdIcmaMZzjnF105SLhu0LvrQqOzUP4Ma7qXxPUgOA5m3LkzqvSmji6XLPIcC3TzZoCPp+XuWQya3r/lxDHX5r4kr58avhiLprCKRLEbkz6fGM4IJ0yp4x9hsie6X6M/YV6WJij7UdmANty408ClIwG2b3dJB37HQmAIPuiKhJdYP1EbUkE/5c8cl9YC8NcG9YARAO0igP4y77N3QL4/7MQZ+b0YuYG6ebkvx5/Ot9oJljUn3Pd1HyQVuiQmRqrVk9KO1ztelGxSGi/CyspA7iX1XJkkBADfonoPFl++6uuxffuHz84TlHEc3XBArc/rwY/gLPkwgQnsk9fadeh/5g6jxiq9u0tpxSn+1C6fRh+rBrzvomsJ8SSxs4iJvS+dyA6rryDWbN2/GorhkMxJxf5IlMCeGFWJPqSnyZk3GnjK/ZrXMBKTMmoyy3Qeam9IxflA/YG1XT05jxk2Fowi+7UE4VRM/DW+6PHA0S83ggMG9P0yySAUXxQtf+bzzRw7u0ITm1XQj7GPZqOKBCHy+mCkbh9BgUGLbREVQlY3q2Z3gKoNfjr5Egt9dnW9ttQMFUNDY6tQWrsn9QwD+A1u9kcuaDlDok9w7MirbymT1kJ35dxg+9vitcOkL5MnkC+q8uXE9/GGEu/QWoeEF4k9O8zHI/luKsAwuWaiC42HMA410aVCA3utbVSU+x/lzilCiVmJfNQ989bmam0ck8Vy5kWQiWGSV+CWnRhg1pg8lc4oa7V7wnlPzM5Vp36El38VfnZAAxaA/A7fHbTaY/lx+jO19gzxTMWTn9J2HaVhdxyQmor8+ugAffI5swGCtUONhbJcOamgZyekZboY1+ioDQkr0SGsz7GgNZRGGVDLSbN/KwtykyhlYtuw54Ga/PilfWE1vp1cRLEQg2RLkY8m7Sw/BikfulW7sP1MyL8LHMdkuS7mTwPu8PVzJ/TOllncw3u/PyVrcJcVjiBP68IXeP74Jo/SWTpSgFRXMhDe1+uN/VuqiCI7RhyAZS4MFHn7PTc605LM7Mqs9hdmtcZQzkUlMx8SRgC/2NoCj4Osk2eD9DGVZP7eVyAbUi3RqDYC7vgK+KDWApw7Q2DD72HM3I+mnQETgpa8x+o1z2jkhvu5NAmKh36jbzoUBiToLYDNwEs6ALg8zQ49PB7j/kcSZR7BF8MDWiLeNNwKv0YZAfOVo61VtUpzp2WAsVfDTf9sJyTl+acJ30z46iAK6bCU82b25RJtanFZdlrqW2reS4R0/A4zsLBva69cCKM85yAq16qsJDzFg6VLT7AUs1laf5JiGtJQiBjzuCOl85c7Pb2VaqVxsWzr5eazqS7MBZrGoU0iSxsSrQHKs/MjEiTrIDjuv8BKsiAusSEXGFuCibtLAk17g0/JP2gYko1PyNleShYLCFSFMJGtn9N07wwDpfhtKtejQnHdyPuPwoEeSAG6UawORmHtZo2dxw+LMWOXrsBom37UQ9Rdbv8i3ARmhP6p2qU1L7FJM9Mdz7UTWP/Bos8EHPzJOcWOn6dK2C14TVM7H X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: f3a04ac4-c047-4de7-c834-08dad1045da8 X-MS-Exchange-CrossTenant-AuthSource: VI1PR0402MB3439.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2022 05:49:51.1200 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zG4gk7q+fFeLbMx7WiBRsW1X0CM4AMkc7C1Eesen0NYWk5EhnpiSNwSzujmVFKPO X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB7655 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add the DT schema for the DWMAC Ethernet controller on NXP S32 Common Chassis. Signed-off-by: Jan Petrous Signed-off-by: Chester Lin --- Changes in v2: - Fix schema issues. - Add minItems to clocks & clock-names. - Replace all sgmii/SGMII terms with pcs/PCS. .../bindings/net/nxp,s32cc-dwmac.yaml | 135 ++++++++++++++++++ 1 file changed, 135 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml diff --git a/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml new file mode 100644 index 000000000000..c6839fd3df40 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2021-2022 NXP +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/nxp,s32cc-dwmac.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NXP S32CC DWMAC Ethernet controller + +maintainers: + - Jan Petrous + - Chester Lin + +allOf: + - $ref: "snps,dwmac.yaml#" + +properties: + compatible: + enum: + - nxp,s32cc-dwmac + + reg: + items: + - description: Main GMAC registers + - description: S32 MAC control registers + + dma-coherent: true + + clocks: + minItems: 5 + items: + - description: Main GMAC clock + - description: Peripheral registers clock + - description: Transmit PCS clock + - description: Transmit RGMII clock + - description: Transmit RMII clock + - description: Transmit MII clock + - description: Receive PCS clock + - description: Receive RGMII clock + - description: Receive RMII clock + - description: Receive MII clock + - description: + PTP reference clock. This clock is used for programming the + Timestamp Addend Register. If not passed then the system + clock will be used. + + clock-names: + minItems: 5 + items: + - const: stmmaceth + - const: pclk + - const: tx_pcs + - const: tx_rgmii + - const: tx_rmii + - const: tx_mii + - const: rx_pcs + - const: rx_rgmii + - const: rx_rmii + - const: rx_mii + - const: ptp_ref + + tx-fifo-depth: + const: 20480 + + rx-fifo-depth: + const: 20480 + +required: + - compatible + - reg + - tx-fifo-depth + - rx-fifo-depth + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + #define S32GEN1_SCMI_CLK_GMAC0_AXI + #define S32GEN1_SCMI_CLK_GMAC0_TX_PCS + #define S32GEN1_SCMI_CLK_GMAC0_TX_RGMII + #define S32GEN1_SCMI_CLK_GMAC0_TX_RMII + #define S32GEN1_SCMI_CLK_GMAC0_TX_MII + #define S32GEN1_SCMI_CLK_GMAC0_RX_PCS + #define S32GEN1_SCMI_CLK_GMAC0_RX_RGMII + #define S32GEN1_SCMI_CLK_GMAC0_RX_RMII + #define S32GEN1_SCMI_CLK_GMAC0_RX_MII + #define S32GEN1_SCMI_CLK_GMAC0_TS + + soc { + #address-cells = <1>; + #size-cells = <1>; + + gmac0: ethernet@4033c000 { + compatible = "nxp,s32cc-dwmac"; + reg = <0x4033c000 0x2000>, /* gmac IP */ + <0x4007C004 0x4>; /* S32 CTRL_STS reg */ + interrupt-parent = <&gic>; + interrupts = ; + interrupt-names = "macirq"; + phy-mode = "rgmii-id"; + tx-fifo-depth = <20480>; + rx-fifo-depth = <20480>; + dma-coherent; + clocks = <&clks S32GEN1_SCMI_CLK_GMAC0_AXI>, + <&clks S32GEN1_SCMI_CLK_GMAC0_AXI>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_PCS>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_RGMII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_RMII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_MII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_PCS>, + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_RGMII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_RMII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_MII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TS>; + clock-names = "stmmaceth", "pclk", + "tx_pcs", "tx_rgmii", "tx_rmii", "tx_mii", + "rx_pcs", "rx_rgmii", "rx_rmii", "rx_mii", + "ptp_ref"; + + gmac0_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + ethernet-phy@4 { + reg = <0x04>; + }; + }; + }; + };