@@ -103,7 +103,8 @@ mlx5_core-$(CONFIG_MLX5_EN_TLS) += en_accel/ktls_stats.o \
en_accel/fs_tcp.o en_accel/ktls.o en_accel/ktls_txrx.o \
en_accel/ktls_tx.o en_accel/ktls_rx.o
-mlx5_core-$(CONFIG_MLX5_EN_NVMEOTCP) += en_accel/fs_tcp.o en_accel/nvmeotcp.o en_accel/nvmeotcp_rxtx.o
+mlx5_core-$(CONFIG_MLX5_EN_NVMEOTCP) += en_accel/fs_tcp.o en_accel/nvmeotcp.o \
+ en_accel/nvmeotcp_rxtx.o en_accel/nvmeotcp_stats.o
mlx5_core-$(CONFIG_MLX5_SW_STEERING) += steering/dr_domain.o steering/dr_table.o \
steering/dr_matcher.o steering/dr_rule.o \
@@ -614,9 +614,15 @@ mlx5e_nvmeotcp_queue_init(struct net_device *netdev,
{
struct nvme_tcp_ddp_config *config = &tconfig->nvmeotcp;
struct mlx5e_priv *priv = netdev_priv(netdev);
+ struct mlx5e_nvmeotcp_sw_stats *sw_stats;
struct mlx5_core_dev *mdev = priv->mdev;
struct mlx5e_nvmeotcp_queue *queue;
int queue_id, err;
+ u32 channel_ix;
+
+ channel_ix = mlx5e_get_channel_ix_from_io_cpu(&priv->channels.params,
+ config->io_cpu);
+ sw_stats = &priv->nvmeotcp->sw_stats;
if (tconfig->type != ULP_DDP_NVME) {
err = -EOPNOTSUPP;
@@ -643,11 +649,11 @@ mlx5e_nvmeotcp_queue_init(struct net_device *netdev,
queue->id = queue_id;
queue->dgst = config->dgst;
queue->pda = config->cpda;
- queue->channel_ix = mlx5e_get_channel_ix_from_io_cpu(&priv->channels.params,
- config->io_cpu);
+ queue->channel_ix = channel_ix;
queue->size = config->queue_size;
queue->max_klms_per_wqe = MLX5E_MAX_KLM_PER_WQE(mdev);
queue->priv = priv;
+ queue->sw_stats = sw_stats;
init_completion(&queue->static_params_done);
err = mlx5e_nvmeotcp_queue_rx_init(queue, config, netdev);
@@ -659,6 +665,7 @@ mlx5e_nvmeotcp_queue_init(struct net_device *netdev,
if (err)
goto destroy_rx;
+ atomic64_inc(&sw_stats->rx_nvmeotcp_sk_add);
write_lock_bh(&sk->sk_callback_lock);
ulp_ddp_set_ctx(sk, queue);
write_unlock_bh(&sk->sk_callback_lock);
@@ -672,6 +679,7 @@ mlx5e_nvmeotcp_queue_init(struct net_device *netdev,
free_queue:
kfree(queue);
out:
+ atomic64_inc(&sw_stats->rx_nvmeotcp_sk_add_fail);
return err;
}
@@ -685,6 +693,8 @@ mlx5e_nvmeotcp_queue_teardown(struct net_device *netdev,
queue = container_of(ulp_ddp_get_ctx(sk), struct mlx5e_nvmeotcp_queue, ulp_ddp_ctx);
+ atomic64_inc(&queue->sw_stats->rx_nvmeotcp_sk_del);
+
WARN_ON(refcount_read(&queue->ref_count) != 1);
mlx5e_nvmeotcp_destroy_rx(priv, queue, mdev);
@@ -816,25 +826,34 @@ mlx5e_nvmeotcp_ddp_setup(struct net_device *netdev,
struct ulp_ddp_io *ddp)
{
struct scatterlist *sg = ddp->sg_table.sgl;
+ struct mlx5e_nvmeotcp_sw_stats *sw_stats;
struct mlx5e_nvmeotcp_queue_entry *nvqt;
struct mlx5e_nvmeotcp_queue *queue;
struct mlx5_core_dev *mdev;
int i, size = 0, count = 0;
+ int ret = 0;
queue = container_of(ulp_ddp_get_ctx(sk),
struct mlx5e_nvmeotcp_queue, ulp_ddp_ctx);
+ sw_stats = queue->sw_stats;
mdev = queue->priv->mdev;
count = dma_map_sg(mdev->device, ddp->sg_table.sgl, ddp->nents,
DMA_FROM_DEVICE);
- if (count <= 0)
- return -EINVAL;
+ if (count <= 0) {
+ ret = -EINVAL;
+ goto ddp_setup_fail;
+ }
- if (WARN_ON(count > mlx5e_get_max_sgl(mdev)))
- return -ENOSPC;
+ if (WARN_ON(count > mlx5e_get_max_sgl(mdev))) {
+ ret = -ENOSPC;
+ goto ddp_setup_fail;
+ }
- if (!mlx5e_nvmeotcp_validate_sgl(sg, count, READ_ONCE(netdev->mtu)))
- return -EOPNOTSUPP;
+ if (!mlx5e_nvmeotcp_validate_sgl(sg, count, READ_ONCE(netdev->mtu))) {
+ ret = -EOPNOTSUPP;
+ goto ddp_setup_fail;
+ }
for (i = 0; i < count; i++)
size += sg_dma_len(&sg[i]);
@@ -846,8 +865,13 @@ mlx5e_nvmeotcp_ddp_setup(struct net_device *netdev,
nvqt->ccid_gen++;
nvqt->sgl_length = count;
mlx5e_nvmeotcp_post_klm_wqe(queue, KLM_UMR, ddp->command_id, count);
-
+ atomic64_inc(&sw_stats->rx_nvmeotcp_ddp_setup);
return 0;
+
+ddp_setup_fail:
+ dma_unmap_sg(mdev->device, ddp->sg_table.sgl, count, DMA_FROM_DEVICE);
+ atomic64_inc(&sw_stats->rx_nvmeotcp_ddp_setup_fail);
+ return ret;
}
void mlx5e_nvmeotcp_ctx_complete(struct mlx5e_icosq_wqe_info *wi)
@@ -894,6 +918,7 @@ mlx5e_nvmeotcp_ddp_teardown(struct net_device *netdev,
q_entry->queue = queue;
mlx5e_nvmeotcp_post_klm_wqe(queue, KLM_INV_UMR, ddp->command_id, 0);
+ atomic64_inc(&queue->sw_stats->rx_nvmeotcp_ddp_teardown);
}
static void
@@ -9,6 +9,15 @@
#include "en.h"
#include "en/params.h"
+struct mlx5e_nvmeotcp_sw_stats {
+ atomic64_t rx_nvmeotcp_sk_add;
+ atomic64_t rx_nvmeotcp_sk_add_fail;
+ atomic64_t rx_nvmeotcp_sk_del;
+ atomic64_t rx_nvmeotcp_ddp_setup;
+ atomic64_t rx_nvmeotcp_ddp_setup_fail;
+ atomic64_t rx_nvmeotcp_ddp_teardown;
+};
+
struct mlx5e_nvmeotcp_queue_entry {
struct mlx5e_nvmeotcp_queue *queue;
u32 sgl_length;
@@ -52,6 +61,7 @@ struct mlx5e_nvmeotcp_queue_handler {
* @sk: The socket used by the NVMe-TCP queue
* @crc_rx: CRC Rx offload indication for this queue
* @priv: mlx5e netdev priv
+ * @sw_stats: Global software statistics for nvmeotcp offload
* @static_params_done: Async completion structure for the initial umr mapping
* synchronization
* @sq_lock: Spin lock for the icosq
@@ -88,6 +98,7 @@ struct mlx5e_nvmeotcp_queue {
u8 crc_rx:1;
/* for ddp invalidate flow */
struct mlx5e_priv *priv;
+ struct mlx5e_nvmeotcp_sw_stats *sw_stats;
/* end of data-path section */
struct completion static_params_done;
@@ -97,6 +108,7 @@ struct mlx5e_nvmeotcp_queue {
};
struct mlx5e_nvmeotcp {
+ struct mlx5e_nvmeotcp_sw_stats sw_stats;
struct ida queue_ids;
struct rhashtable queue_hash;
bool enabled;
@@ -113,6 +125,7 @@ void mlx5e_nvmeotcp_ddp_inv_done(struct mlx5e_icosq_wqe_info *wi);
void mlx5e_nvmeotcp_ctx_complete(struct mlx5e_icosq_wqe_info *wi);
static inline void mlx5e_nvmeotcp_init_rx(struct mlx5e_priv *priv) {}
void mlx5e_nvmeotcp_cleanup_rx(struct mlx5e_priv *priv);
+int mlx5e_nvmeotcp_get_stats(struct mlx5e_priv *priv, struct ethtool_ulp_ddp_stats *stats);
extern const struct ulp_ddp_dev_ops mlx5e_nvmeotcp_ops;
#else
@@ -122,5 +135,8 @@ static inline void mlx5e_nvmeotcp_cleanup(struct mlx5e_priv *priv) {}
static inline int set_ulp_ddp_nvme_tcp(struct net_device *dev, bool en) { return -EOPNOTSUPP; }
static inline void mlx5e_nvmeotcp_init_rx(struct mlx5e_priv *priv) {}
static inline void mlx5e_nvmeotcp_cleanup_rx(struct mlx5e_priv *priv) {}
+static inline int mlx5e_nvmeotcp_get_stats(struct mlx5e_priv *priv,
+ struct ethtool_ulp_ddp_stats *stats)
+{ return 0; }
#endif
#endif /* __MLX5E_NVMEOTCP_H__ */
@@ -111,6 +111,7 @@ mlx5e_nvmeotcp_rebuild_rx_skb_nonlinear(struct mlx5e_rq *rq, struct sk_buff *skb
int ccoff, cclen, hlen, ccid, remaining, fragsz, to_copy = 0;
struct net_device *netdev = rq->netdev;
struct mlx5e_priv *priv = netdev_priv(netdev);
+ struct mlx5e_rq_stats *stats = rq->stats;
struct mlx5e_nvmeotcp_queue_entry *nqe;
skb_frag_t org_frags[MAX_SKB_FRAGS];
struct mlx5e_nvmeotcp_queue *queue;
@@ -122,12 +123,14 @@ mlx5e_nvmeotcp_rebuild_rx_skb_nonlinear(struct mlx5e_rq *rq, struct sk_buff *skb
queue = mlx5e_nvmeotcp_get_queue(priv->nvmeotcp, queue_id);
if (unlikely(!queue)) {
dev_kfree_skb_any(skb);
+ stats->nvmeotcp_drop++;
return false;
}
cqe128 = container_of(cqe, struct mlx5e_cqe128, cqe64);
if (cqe_is_nvmeotcp_resync(cqe)) {
nvmeotcp_update_resync(queue, cqe128);
+ stats->nvmeotcp_resync++;
mlx5e_nvmeotcp_put_queue(queue);
return true;
}
@@ -201,7 +204,8 @@ mlx5e_nvmeotcp_rebuild_rx_skb_nonlinear(struct mlx5e_rq *rq, struct sk_buff *skb
org_nr_frags,
frag_index);
}
-
+ stats->nvmeotcp_packets++;
+ stats->nvmeotcp_bytes += cclen;
mlx5e_nvmeotcp_put_queue(queue);
return true;
}
@@ -213,6 +217,7 @@ mlx5e_nvmeotcp_rebuild_rx_skb_linear(struct mlx5e_rq *rq, struct sk_buff *skb,
int ccoff, cclen, hlen, ccid, remaining, fragsz, to_copy = 0;
struct net_device *netdev = rq->netdev;
struct mlx5e_priv *priv = netdev_priv(netdev);
+ struct mlx5e_rq_stats *stats = rq->stats;
struct mlx5e_nvmeotcp_queue_entry *nqe;
struct mlx5e_nvmeotcp_queue *queue;
struct mlx5e_cqe128 *cqe128;
@@ -222,12 +227,14 @@ mlx5e_nvmeotcp_rebuild_rx_skb_linear(struct mlx5e_rq *rq, struct sk_buff *skb,
queue = mlx5e_nvmeotcp_get_queue(priv->nvmeotcp, queue_id);
if (unlikely(!queue)) {
dev_kfree_skb_any(skb);
+ stats->nvmeotcp_drop++;
return false;
}
cqe128 = container_of(cqe, struct mlx5e_cqe128, cqe64);
if (cqe_is_nvmeotcp_resync(cqe)) {
nvmeotcp_update_resync(queue, cqe128);
+ stats->nvmeotcp_resync++;
mlx5e_nvmeotcp_put_queue(queue);
return true;
}
@@ -301,6 +308,8 @@ mlx5e_nvmeotcp_rebuild_rx_skb_linear(struct mlx5e_rq *rq, struct sk_buff *skb,
hlen + cclen, remaining);
}
+ stats->nvmeotcp_packets++;
+ stats->nvmeotcp_bytes += cclen;
mlx5e_nvmeotcp_put_queue(queue);
return true;
}
new file mode 100644
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
+// Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.
+
+#include "en_accel/nvmeotcp.h"
+
+struct ethtool_counter_map {
+ size_t eth_offset;
+ size_t mlx_offset;
+};
+
+#define DECLARE_ULP_SW_STAT(fld) \
+ { offsetof(struct ethtool_ulp_ddp_stats, fld), \
+ offsetof(struct mlx5e_nvmeotcp_sw_stats, fld) }
+
+#define DECLARE_ULP_RQ_STAT(fld) \
+ { offsetof(struct ethtool_ulp_ddp_stats, rx_ ## fld), \
+ offsetof(struct mlx5e_rq_stats, fld) }
+
+#define READ_CTR_ATOMIC64(ptr, dsc, i) \
+ atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].mlx_offset))
+
+#define READ_CTR(ptr, desc, i) \
+ (*((u64 *)((char *)(ptr) + (desc)[i].mlx_offset)))
+
+#define SET_ULP_STAT(ptr, desc, i, val) \
+ (*(u64 *)((char *)(ptr) + (desc)[i].eth_offset) = (val))
+
+/* Global counters */
+static const struct ethtool_counter_map sw_stats_desc[] = {
+ DECLARE_ULP_SW_STAT(rx_nvmeotcp_sk_add),
+ DECLARE_ULP_SW_STAT(rx_nvmeotcp_sk_del),
+ DECLARE_ULP_SW_STAT(rx_nvmeotcp_ddp_setup),
+ DECLARE_ULP_SW_STAT(rx_nvmeotcp_ddp_setup_fail),
+ DECLARE_ULP_SW_STAT(rx_nvmeotcp_ddp_teardown),
+};
+
+/* Per-rx-queue counters */
+static const struct ethtool_counter_map rq_stats_desc[] = {
+ DECLARE_ULP_RQ_STAT(nvmeotcp_drop),
+ DECLARE_ULP_RQ_STAT(nvmeotcp_resync),
+ DECLARE_ULP_RQ_STAT(nvmeotcp_packets),
+ DECLARE_ULP_RQ_STAT(nvmeotcp_bytes),
+};
+
+int mlx5e_nvmeotcp_get_stats(struct mlx5e_priv *priv, struct ethtool_ulp_ddp_stats *stats)
+{
+ unsigned int i, ch, n = 0;
+
+ if (!priv->nvmeotcp)
+ return 0;
+
+ for (i = 0; i < ARRAY_SIZE(sw_stats_desc); i++, n++)
+ SET_ULP_STAT(stats, sw_stats_desc, i,
+ READ_CTR_ATOMIC64(&priv->nvmeotcp->sw_stats, sw_stats_desc, i));
+
+ for (i = 0; i < ARRAY_SIZE(rq_stats_desc); i++, n++) {
+ u64 sum = 0;
+
+ for (ch = 0; ch < priv->stats_nch; ch++)
+ sum += READ_CTR(&priv->channel_stats[ch]->rq, rq_stats_desc, i);
+
+ SET_ULP_STAT(stats, rq_stats_desc, i, sum);
+ }
+
+ return n;
+}
@@ -2400,6 +2400,16 @@ static void mlx5e_get_rmon_stats(struct net_device *netdev,
}
#ifdef CONFIG_MLX5_EN_NVMEOTCP
+static int mlx5e_get_ulp_ddp_stats(struct net_device *netdev,
+ struct ethtool_ulp_ddp_stats *stats)
+{
+ struct mlx5e_priv *priv = netdev_priv(netdev);
+
+ mlx5e_stats_ulp_ddp_get(priv, stats);
+
+ return 0;
+}
+
static int mlx5e_set_ulp_ddp_capabilities(struct net_device *netdev, unsigned long *new_caps)
{
struct mlx5e_priv *priv = netdev_priv(netdev);
@@ -2501,6 +2511,7 @@ const struct ethtool_ops mlx5e_ethtool_ops = {
.get_rmon_stats = mlx5e_get_rmon_stats,
.get_link_ext_stats = mlx5e_get_link_ext_stats,
#ifdef CONFIG_MLX5_EN_NVMEOTCP
+ .get_ulp_ddp_stats = mlx5e_get_ulp_ddp_stats,
.set_ulp_ddp_capabilities = mlx5e_set_ulp_ddp_capabilities,
#endif
};
@@ -2497,3 +2497,10 @@ unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv)
{
return ARRAY_SIZE(mlx5e_nic_stats_grps);
}
+
+/* ULP DDP stats */
+
+void mlx5e_stats_ulp_ddp_get(struct mlx5e_priv *priv, struct ethtool_ulp_ddp_stats *stats)
+{
+ mlx5e_nvmeotcp_get_stats(priv, stats);
+}
@@ -128,6 +128,7 @@ void mlx5e_stats_rmon_get(struct mlx5e_priv *priv,
const struct ethtool_rmon_hist_range **ranges);
void mlx5e_get_link_ext_stats(struct net_device *dev,
struct ethtool_link_ext_stats *stats);
+void mlx5e_stats_ulp_ddp_get(struct mlx5e_priv *priv, struct ethtool_ulp_ddp_stats *stats);
/* Concrete NIC Stats */
@@ -395,6 +396,12 @@ struct mlx5e_rq_stats {
u64 tls_resync_res_skip;
u64 tls_err;
#endif
+#ifdef CONFIG_MLX5_EN_NVMEOTCP
+ u64 nvmeotcp_drop;
+ u64 nvmeotcp_resync;
+ u64 nvmeotcp_packets;
+ u64 nvmeotcp_bytes;
+#endif
};
struct mlx5e_sq_stats {