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[v2] LoongArch: BPF: Use 4 instructions for function address in JIT

Message ID 20230214152633.2265699-1-hengqi.chen@gmail.com (mailing list archive)
State Accepted
Commit 64f50f6575721ef03d001e907455cbe3baa2a5b1
Delegated to: BPF
Headers show
Series [v2] LoongArch: BPF: Use 4 instructions for function address in JIT | expand

Checks

Context Check Description
netdev/tree_selection success Not a local patch
bpf/vmtest-bpf-next-PR success PR summary
bpf/vmtest-bpf-next-VM_Test-11 success Logs for test_maps on s390x with gcc
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bpf/vmtest-bpf-next-VM_Test-26 success Logs for test_progs_no_alu32_parallel on s390x with gcc
bpf/vmtest-bpf-next-VM_Test-16 success Logs for test_progs on s390x with gcc
bpf/vmtest-bpf-next-VM_Test-31 success Logs for test_progs_parallel on s390x with gcc
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bpf/vmtest-bpf-next-VM_Test-24 success Logs for test_progs_no_alu32_parallel on aarch64 with gcc
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bpf/vmtest-bpf-next-VM_Test-38 success Logs for test_verifier on x86_64 with llvm-16
bpf/vmtest-bpf-next-VM_Test-9 success Logs for test_maps on aarch64 with gcc
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bpf/vmtest-bpf-next-VM_Test-12 success Logs for test_maps on x86_64 with gcc
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Commit Message

Hengqi Chen Feb. 14, 2023, 3:26 p.m. UTC 
This patch fixes the following issue of function calls in JIT, like:

  [   29.346981] multi-func JIT bug 105 != 103

The issus can be reproduced by running the "inline simple bpf_loop call"
verifier test.

This is because we are emiting 2-4 instructions for 64-bit immediate moves.
During the first pass of JIT, the placeholder address is zero, emiting two
instructions for it. In the extra pass, the function address is in XKVRANGE,
emiting four instructions for it. This change the instruction index in
JIT context. Let's always use 4 instructions for function address in JIT.
So that the instruction sequences don't change between the first pass and
the extra pass for function calls.

Fixes: 5dc615520c4d ("LoongArch: Add BPF JIT support")
Signed-off-by: Hengqi Chen <hengqi.chen@gmail.com>
---
 arch/loongarch/net/bpf_jit.c |  2 +-
 arch/loongarch/net/bpf_jit.h | 21 +++++++++++++++++++++
 2 files changed, 22 insertions(+), 1 deletion(-)

--
2.31.1

Comments

Tiezhu Yang Feb. 16, 2023, 6:52 a.m. UTC | #1 
On 02/14/2023 11:26 PM, Hengqi Chen wrote:
> This patch fixes the following issue of function calls in JIT, like:
>
>   [   29.346981] multi-func JIT bug 105 != 103
>
> The issus can be reproduced by running the "inline simple bpf_loop call"
> verifier test.
>
> This is because we are emiting 2-4 instructions for 64-bit immediate moves.
> During the first pass of JIT, the placeholder address is zero, emiting two
> instructions for it. In the extra pass, the function address is in XKVRANGE,
> emiting four instructions for it. This change the instruction index in
> JIT context. Let's always use 4 instructions for function address in JIT.
> So that the instruction sequences don't change between the first pass and
> the extra pass for function calls.
>
> Fixes: 5dc615520c4d ("LoongArch: Add BPF JIT support")
> Signed-off-by: Hengqi Chen <hengqi.chen@gmail.com>

Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn>
patchwork-bot+netdevbpf@kernel.org Feb. 17, 2023, 4:50 p.m. UTC | #2 
Hello:

This patch was applied to bpf/bpf-next.git (master)
by Daniel Borkmann <daniel@iogearbox.net>:

On Tue, 14 Feb 2023 15:26:33 +0000 you wrote:
> This patch fixes the following issue of function calls in JIT, like:
> 
>   [   29.346981] multi-func JIT bug 105 != 103
> 
> The issus can be reproduced by running the "inline simple bpf_loop call"
> verifier test.
> 
> [...]

Here is the summary with links:
  - [v2] LoongArch: BPF: Use 4 instructions for function address in JIT
    https://git.kernel.org/bpf/bpf-next/c/64f50f657572

You are awesome, thank you!
diff mbox series

Patch

diff --git a/arch/loongarch/net/bpf_jit.c b/arch/loongarch/net/bpf_jit.c
index c4b1947ebf76..288003a9f0ca 100644
--- a/arch/loongarch/net/bpf_jit.c
+++ b/arch/loongarch/net/bpf_jit.c
@@ -841,7 +841,7 @@  static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, bool ext
 		if (ret < 0)
 			return ret;

-		move_imm(ctx, t1, func_addr, is32);
+		move_addr(ctx, t1, func_addr);
 		emit_insn(ctx, jirl, t1, LOONGARCH_GPR_RA, 0);
 		move_reg(ctx, regmap[BPF_REG_0], LOONGARCH_GPR_A0);
 		break;
diff --git a/arch/loongarch/net/bpf_jit.h b/arch/loongarch/net/bpf_jit.h
index ca708024fdd3..c335dc4eed37 100644
--- a/arch/loongarch/net/bpf_jit.h
+++ b/arch/loongarch/net/bpf_jit.h
@@ -82,6 +82,27 @@  static inline void emit_sext_32(struct jit_ctx *ctx, enum loongarch_gpr reg, boo
 	emit_insn(ctx, addiw, reg, reg, 0);
 }

+static inline void move_addr(struct jit_ctx *ctx, enum loongarch_gpr rd, u64 addr)
+{
+	u64 imm_11_0, imm_31_12, imm_51_32, imm_63_52;
+
+	/* lu12iw rd, imm_31_12 */
+	imm_31_12 = (addr >> 12) & 0xfffff;
+	emit_insn(ctx, lu12iw, rd, imm_31_12);
+
+	/* ori rd, rd, imm_11_0 */
+	imm_11_0 = addr & 0xfff;
+	emit_insn(ctx, ori, rd, rd, imm_11_0);
+
+	/* lu32id rd, imm_51_32 */
+	imm_51_32 = (addr >> 32) & 0xfffff;
+	emit_insn(ctx, lu32id, rd, imm_51_32);
+
+	/* lu52id rd, rd, imm_63_52 */
+	imm_63_52 = (addr >> 52) & 0xfff;
+	emit_insn(ctx, lu52id, rd, rd, imm_63_52);
+}
+
 static inline void move_imm(struct jit_ctx *ctx, enum loongarch_gpr rd, long imm, bool is32)
 {
 	long imm_11_0, imm_31_12, imm_51_32, imm_63_52, imm_51_0, imm_51_31;