@@ -28,6 +28,65 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ snps,route-up;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ snps,route-ptp;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ snps,route-avcp;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ snps,priority = <0xc>;
+ };
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ snps,tx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3e800>;
+ snps,low_credit = <0xffc18000>;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3e800>;
+ snps,low_credit = <0xffc18000>;
+ };
+ };
};
&apps_rsc {
@@ -151,6 +210,68 @@ vreg_l8g: ldo8 {
};
};
+ðernet0 {
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+
+ max-speed = <1000>;
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii-txid";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet0_default>;
+
+ status = "okay";
+
+ mdio {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ compatible = "snps,dwmac-mdio";
+
+ /* Marvell 88EA1512 */
+ rgmii_phy: phy@8 {
+ reg = <0x8>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts-extended = <&tlmm 127 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = <&pmm8540c_gpios 1 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <11000>;
+ reset-deassert-us = <70000>;
+
+ device_type = "ethernet-phy";
+
+ /* Set to RGMII_SGMII mode and soft reset. Turn off auto-negotiation
+ * from userspace to talk to the switch on the SGMII side of things
+ */
+ marvell,reg-init =
+ /* Set MODE[2:0] to RGMII_SGMII */
+ <0x12 0x14 0xfff8 0x4>,
+ /* Soft reset required after changing MODE[2:0] */
+ <0x12 0x14 0x7fff 0x8000>;
+ };
+ };
+};
+
+ðernet1 {
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+
+ max-speed = <1000>;
+ phy-mode = "rgmii-txid";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet1_default>;
+
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_default>;
@@ -316,6 +437,66 @@ &xo_board_clk {
/* PINCTRL */
&tlmm {
+ ethernet0_default: ethernet0-default-state {
+ mdc-pins {
+ pins = "gpio175";
+ function = "rgmii_0";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ mdio-pins {
+ pins = "gpio176";
+ function = "rgmii_0";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ rgmii-tx-pins {
+ pins = "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188";
+ function = "rgmii_0";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ rgmii-rx-pins {
+ pins = "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182";
+ function = "rgmii_0";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ ethernet1_default: ethernet1-default-state {
+ mdc-pins {
+ pins = "gpio97";
+ function = "rgmii_1";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ mdio-pins {
+ pins = "gpio98";
+ function = "rgmii_1";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ rgmii-tx-pins {
+ pins = "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110";
+ function = "rgmii_1";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ rgmii-rx-pins {
+ pins = "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104";
+ function = "rgmii_1";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
i2c0_default: i2c0-default-state {
/* To USB7002T-I/KDXVA0 USB hub (SIP1 only) */
pins = "gpio135", "gpio136";
Enable both the MACs found on the board. ethernet0 and ethernet1 both ultimately go to a series of on board switches which aren't managed by this processor. ethernet0 is connected to a Marvell 88EA1512 phy via RGMII. That goes to the series of switches via SGMII on the "media" side of the phy. RGMII_SGMII mode is enabled via devicetree register descriptions. The switch on the "media" side has auto-negotiation disabled, so configuration from userspace similar to: ethtool -s eth0 autoneg off speed 1000 duplex full is necessary to get traffic flowing on that interface. ethernet1 is in a mac2mac/fixed-link configuration going to the same series of switches directly via RGMII. Signed-off-by: Andrew Halaney <ahalaney@redhat.com> --- Changes since v1: * None arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 181 ++++++++++++++++++++++ 1 file changed, 181 insertions(+)