[v2] bpf: Fix mask generation for 32-bit narrow loads of 64-bit fields

Commit Message

Will Deacon May 18, 2023, 10:25 a.m. UTC

A narrow load from a 64-bit context field results in a 64-bit load
followed potentially by a 64-bit right-shift and then a bitwise AND
operation to extract the relevant data.

In the case of a 32-bit access, an immediate mask of 0xffffffff is used
to construct a 64-bit BPP_AND operation which then sign-extends the mask
value and effectively acts as a glorified no-op. For example:

0:	61 10 00 00 00 00 00 00	r0 = *(u32 *)(r1 + 0)

results in the following code generation for a 64-bit field:

	ldr	x7, [x7]	// 64-bit load
	mov	x10, #0xffffffffffffffff
	and	x7, x7, x10

Fix the mask generation so that narrow loads always perform a 32-bit AND
operation:

	ldr	x7, [x7]	// 64-bit load
	mov	w10, #0xffffffff
	and	w7, w7, w10

Cc: Alexei Starovoitov <[e-mail]>
Cc: Daniel Borkmann <[e-mail]>
Cc: John Fastabend <[e-mail]>
Cc: Krzesimir Nowak <[e-mail]>
Cc: Andrey Ignatov <[e-mail]>
Acked-by: Yonghong Song <[e-mail]>
Fixes: 31fd85816dbe ("bpf: permits narrower load from bpf program context fields")
Signed-off-by: Will Deacon <[e-mail]>
---

v2: Improve commit message and add Acked-by.

 kernel/bpf/verifier.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Alexei Starovoitov May 19, 2023, 6:03 p.m. UTC | #1

On Thu, May 18, 2023 at 3:25 AM Will Deacon <[e-mail]> wrote:
>
> A narrow load from a 64-bit context field results in a 64-bit load
> followed potentially by a 64-bit right-shift and then a bitwise AND
> operation to extract the relevant data.
>
> In the case of a 32-bit access, an immediate mask of 0xffffffff is used
> to construct a 64-bit BPP_AND operation which then sign-extends the mask
> value and effectively acts as a glorified no-op. For example:
>
> 0:      61 10 00 00 00 00 00 00 r0 = *(u32 *)(r1 + 0)
>
> results in the following code generation for a 64-bit field:
>
>         ldr     x7, [x7]        // 64-bit load
>         mov     x10, #0xffffffffffffffff
>         and     x7, x7, x10
>
> Fix the mask generation so that narrow loads always perform a 32-bit AND
> operation:
>
>         ldr     x7, [x7]        // 64-bit load
>         mov     w10, #0xffffffff
>         and     w7, w7, w10
>
> Cc: Alexei Starovoitov <[e-mail]>
> Cc: Daniel Borkmann <[e-mail]>
> Cc: John Fastabend <[e-mail]>
> Cc: Krzesimir Nowak <[e-mail]>
> Cc: Andrey Ignatov <[e-mail]>
> Acked-by: Yonghong Song <[e-mail]>
> Fixes: 31fd85816dbe ("bpf: permits narrower load from bpf program context fields")
> Signed-off-by: Will Deacon <[e-mail]>

Thanks for the fix! Applied to bpf tree.

Patch

diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index fbcf5a4e2fcd..5871aa78d01a 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -17033,7 +17033,7 @@  static int convert_ctx_accesses(struct bpf_verifier_env *env)
 					insn_buf[cnt++] = BPF_ALU64_IMM(BPF_RSH,
 									insn->dst_reg,
 									shift);
-				insn_buf[cnt++] = BPF_ALU64_IMM(BPF_AND, insn->dst_reg,
+				insn_buf[cnt++] = BPF_ALU32_IMM(BPF_AND, insn->dst_reg,
 								(1ULL << size * 8) - 1);
 			}
 		}