Message ID | 20230526152348.70781-5-Parthiban.Veerasooran@microchip.com (mailing list archive) |
---|---|
State | Accepted |
Commit | 1d7650b8ce6041be4ea0436ad7a69c057b4d22f8 |
Delegated to: | Netdev Maintainers |
Headers | show |
Series | microchip_t1s: Update on Microchip 10BASE-T1S PHY driver | expand |
Context | Check | Description |
---|---|---|
netdev/series_format | success | Posting correctly formatted |
netdev/tree_selection | success | Clearly marked for net-next |
netdev/fixes_present | success | Fixes tag not required for -next series |
netdev/header_inline | success | No static functions without inline keyword in header files |
netdev/build_32bit | success | Errors and warnings before: 8 this patch: 8 |
netdev/cc_maintainers | success | CCed 8 of 8 maintainers |
netdev/build_clang | success | Errors and warnings before: 8 this patch: 8 |
netdev/verify_signedoff | success | Signed-off-by tag matches author and committer |
netdev/deprecated_api | success | None detected |
netdev/check_selftest | success | No net selftest shell script |
netdev/verify_fixes | success | No Fixes tag |
netdev/build_allmodconfig_warn | success | Errors and warnings before: 8 this patch: 8 |
netdev/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 33 lines checked |
netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
netdev/source_inline | success | Was 0 now: 0 |
On Fri, May 26, 2023 at 08:53:46PM +0530, Parthiban Veerasooran wrote: > As per the datasheet DS-LAN8670-1-2-60001573C.pdf, the Reset Complete > status bit in the STS2 register has to be checked before proceeding to > the initial configuration. Reading STS2 register will also clear the > Reset Complete interrupt which is non-maskable. > > Reviewed-by: Andrew Lunn <andrew@lunn.ch> > Signed-off-by: Parthiban Veerasooran <Parthiban.Veerasooran@microchip.com> > --- Reviewed-by: Ramón Nordin Rodriguez <ramon.nordin.rodriguez@ferroamp.se> Tested-by: Ramón Nordin Rodriguez <ramon.nordin.rodriguez@ferroamp.se>
diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1s.c index 7abecad28bf1..0ecef87e5882 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -14,6 +14,9 @@ #define LAN867X_REG_IRQ_1_CTL 0x001C #define LAN867X_REG_IRQ_2_CTL 0x001D +#define LAN867X_REG_STS2 0x0019 + +#define LAN867x_RESET_COMPLETE_STS BIT(11) /* The arrays below are pulled from the following table from AN1699 * Access MMD Address Value Mask @@ -53,6 +56,24 @@ static int lan867x_revb1_config_init(struct phy_device *phydev) { int err; + /* The chip completes a reset in 3us, we might get here earlier than + * that, as an added margin we'll conditionally sleep 5us. + */ + err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); + if (err < 0) + return err; + + if (!(err & LAN867x_RESET_COMPLETE_STS)) { + udelay(5); + err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); + if (err < 0) + return err; + if (!(err & LAN867x_RESET_COMPLETE_STS)) { + phydev_err(phydev, "PHY reset failed\n"); + return -ENODEV; + } + } + /* Reference to AN1699 * https://ww1.microchip.com/downloads/aemDocuments/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8670-1-2-config-60001699.pdf * AN1699 says Read, Modify, Write, but the Write is not required if the