@@ -76,6 +76,10 @@
#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6)
#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5)
+/* MAC_CTRL_REG bits */
+#define ETHQOS_MAC_CTRL_SPEED_MODE BIT(14)
+#define ETHQOS_MAC_CTRL_PORT_SEL BIT(15)
+
struct ethqos_emac_por {
unsigned int offset;
unsigned int value;
@@ -92,6 +96,7 @@ struct ethqos_emac_driver_data {
struct qcom_ethqos {
struct platform_device *pdev;
void __iomem *rgmii_base;
+ void __iomem *mac_base;
int (*configure_func)(struct qcom_ethqos *ethqos);
unsigned int rgmii_clk_rate;
@@ -561,6 +566,33 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos)
return 0;
}
+static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
+{
+ int val;
+
+ val = readl(ethqos->mac_base + MAC_CTRL_REG);
+
+ switch (ethqos->speed) {
+ case SPEED_1000:
+ val &= ~ETHQOS_MAC_CTRL_PORT_SEL;
+ rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
+ RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
+ RGMII_IO_MACRO_CONFIG2);
+ break;
+ case SPEED_100:
+ val |= ETHQOS_MAC_CTRL_PORT_SEL | ETHQOS_MAC_CTRL_SPEED_MODE;
+ break;
+ case SPEED_10:
+ val |= ETHQOS_MAC_CTRL_PORT_SEL;
+ val &= ~ETHQOS_MAC_CTRL_SPEED_MODE;
+ break;
+ }
+
+ writel(val, ethqos->mac_base + MAC_CTRL_REG);
+
+ return val;
+}
+
static int ethqos_configure(struct qcom_ethqos *ethqos)
{
return ethqos->configure_func(ethqos);
@@ -673,6 +705,9 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
case PHY_INTERFACE_MODE_RGMII_TXID:
ethqos->configure_func = ethqos_configure_rgmii;
break;
+ case PHY_INTERFACE_MODE_SGMII:
+ ethqos->configure_func = ethqos_configure_sgmii;
+ break;
case -ENODEV:
ret = -ENODEV;
goto out_config_dt;
@@ -688,6 +723,8 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
goto out_config_dt;
}
+ ethqos->mac_base = stmmac_res.addr;
+
data = of_device_get_match_data(dev);
ethqos->por = data->por;
ethqos->num_por = data->num_por;