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Miller" , Rahul Rameshbabu Subject: [PATCH v3 1/9] ptp: Clarify ptp_clock_info .adjphase expects an internal servo to be used Date: Mon, 12 Jun 2023 14:14:52 -0700 Message-Id: <20230612211500.309075-2-rrameshbabu@nvidia.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230612211500.309075-1-rrameshbabu@nvidia.com> References: <20230612211500.309075-1-rrameshbabu@nvidia.com> X-ClientProxiedBy: BYAPR01CA0004.prod.exchangelabs.com (2603:10b6:a02:80::17) To BYAPR12MB2743.namprd12.prod.outlook.com (2603:10b6:a03:61::28) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BYAPR12MB2743:EE_|MW6PR12MB8733:EE_ X-MS-Office365-Filtering-Correlation-Id: ed3a1de6-0886-4fa5-a18f-08db6b8a2533 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mQi7d9WynrUBSXrOTwQsxtdsCmOMXKyrT0XQJIUH0/jg7gNs29T8NEhhZv9Ys1O9j01GoHbEAjt/HZWo7kxjzMqyQrRFVZ8Of3e9qyct3NrmrOE5ceYA9pt/h+7BzK0AT75lEA3IEo0w67A5gtwRB3E9iI1r59KwAL++uIiW2FcoL7hzNzN090qIxVpbRaWSW5ko4n0vsGnaOb4nPFIY9812AA1JqoFss+qADjPOQ962Najw5NMMkweim6JRHwWC3XOi5RZwBkrhOghk7B+BfZAKOLXS02/RnXWwMLXvfJrFwqFyaVp+aRdFq3VKVy4ZsHP5SGAQvMMumzCFdeQwYq0WV5ul6YMLXCupN/YUDxaFaVwLcJtINqsS9hj3xbA0VR69UQ4twSVIsaw03QA9l6eFQxoy8VI3Nuyqoixbt41ZEeflRFnO0dz8oY3cz9NepA6XlUY5RjVPnrum1/qh2HUCrIbytWWgb8M9ZE75Y+aforc9hT/702uwSu1fnqQlMtndrnSoW3cHp2M8xH3OCbdYxO5AFm1Wx3HxeEKnXsxzApHLu6hae5kJ5wdjakqv7Yx3cuby1QZc5pFyMAl32hYpxtUDrCA9OiCw+CUUEzvZrV+ipKy/Oc/E0FvShNPD X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BYAPR12MB2743.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(4636009)(366004)(39860400002)(396003)(346002)(136003)(376002)(451199021)(6916009)(4326008)(66946007)(66476007)(66556008)(36756003)(186003)(478600001)(54906003)(2616005)(2906002)(8676002)(316002)(41300700001)(107886003)(86362001)(6486002)(6666004)(6506007)(1076003)(8936002)(83380400001)(5660300002)(26005)(38100700002)(6512007)(142923001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zMd2p2QEUhVA8VL8gfv/GX0Tr8wdmonJbK/GZkvAuP/HKu7AC10HgThGnhWnAOeWlWgKTEx2C1J+OmHhgEVIO/HBX0T2iU8J3ZTlJ+cgagVns/9JXIfk+LLYibzSIXajZi1Hyfg4hzNnW7rLJhSWUyiJSwEelEVgjHWhCuRguaOsPPHUzDK7WOB5OONujAmJ8GXP8Qrn325jZuU3o/2VOk25ymUU4E7sheAo3KSLRkEDUrkWiJ3zlCTPxjBEPu8R+SV0muhWRl7T6Q6yMiNEfi5QYWhHlbcULX212wjnM215/e0OSIagVYwTsRblNTsWWk4MVvuh9a5D8o2cJQakKrK0ATGdxMWiHY6SJ0I0vdvysk/CsIKtwJfB9CuLPsLgXWP7Wosrt48GU21jfX6O2ikL7in8IfrfC0JqcQZIqYCnJ60IbGviwUcJbZRfcQjuE6I/O3rOG8SIwv9YlWwJcc8iL7qogcox1LsLM3QkmooTDz3DO4lRboWpsGWpEsHoWo+6W8l0kTTUcwEZVx7BwoX7r9BNZbEvsQKxV60b24pRc1F3AgRPqu/OoysPDc8IIklTxh1nAGSvxFA+vDLxDTh4JBsZeBpKapcN3VZRBKQFX7B5Q00aXo6AIY3mgzmpHvLPFwOElSpGjoMkBZtxMo73GK4MS54qxDoCQ09sjn4Wefg3RnvaMYlvl+qKEmLTw69MM6OdeP7UikuVgWguoC32v0XmjAY+BkOJNjqeemTl1HFgTvYmbwxSbQ1PFkR2P9uwOaZ+On5xGWdTWaFB/LHZ7k0xUJjfBdTOeaT77XTN8SrQ/Wg3QwPh/Ufn8perqrdGzi0GRWgNrluMdHiBFbZKcGhCfkq51OgvLXu8nkRBpU+l+pQ2NMjU2imA7VzUdmBStnsNF3tZPFBbjhas/BcWdqP0J7SW/srB6nFIrj7of0beiyHqoTt3ZB89SgYdRzc/oWmu6e7bbHEA6I4iEhbWOadpsMYdzaV/Ekl8+V/Fu2awDBm9xXwh66W/ygEVj79QOpGyVdd1+GIeWljv7NDL8otPjkStdkv2X1NOWkY5szjHl79sb51Ml6iMshP6CrHXzyMV146RRIaU2K8G9JVypnjKOfUz/O8WtAMr3SWYhd8HcBzr5TRGmmudzFN4qPNbh54/GbddaU1U1Ie1WUknKrUF9gfenmNObSZhHw6AkmORW2bHoEDXKlLKvxnHCGQKc3jIfTKTywLP4XnlHlgH30zgaq8Dv8TNyKX8Yl3v9Ri9/i6DlJrk2Ckddc4MpFTanGNxRQFRN9t9pmdgonz3/S2zxJR/uxtKMy7MQVvDloUELkNkdVUIJdl4sk8uRfZiHDPJ0e1Gmp8pkjyOSw2FmvoSMlZg6T+tymOt/r0IiWfTq47UBCv/5/pGTgwD2E+7vRjnbSF+p861FBBQn9xiDHfsDxMu5NRi2bDmANJr9+kHpnf/lvIOGorMOfhzAC+6Cc7pmclNx1Eifm9bJqI8i3toqsvva6FuWLsCRaHZ+XN+uMWNbenxpcO2WxshZCedJvB+kNDEpgwiVaz9fAMJMml616NdEVb2nVILRkwBZdvTktpxyGZbJQzdwiUAqu13zN2oeSIsP3y/aM05UQ== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ed3a1de6-0886-4fa5-a18f-08db6b8a2533 X-MS-Exchange-CrossTenant-AuthSource: BYAPR12MB2743.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2023 21:15:27.8160 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5KZ67IQCW5pvH0Cd6ork2v5kfq612fJ7rCRLPLjzxj8m4Eb5dq+BVrA6xzuWIuCQ2Tt3KWFq7BbTwz8u7k/4fw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8733 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net .adjphase expects a PHC to use an internal servo algorithm to correct the provided phase offset target in the callback. Implementation of the internal servo algorithm are defined by the individual devices. Cc: Jakub Kicinski Cc: Richard Cochran Signed-off-by: Rahul Rameshbabu Acked-by: Richard Cochran --- Notes: Changes: v2->v1: * Removes arbitrary rule that the PHC servo must restore the frequency to the value used in the last .adjfine call if any other PHC operation is used after a .adjphase operation. Documentation/driver-api/ptp.rst | 16 ++++++++++++++++ include/linux/ptp_clock_kernel.h | 6 ++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/Documentation/driver-api/ptp.rst b/Documentation/driver-api/ptp.rst index 664838ae7776..4552a1f20488 100644 --- a/Documentation/driver-api/ptp.rst +++ b/Documentation/driver-api/ptp.rst @@ -73,6 +73,22 @@ Writing clock drivers class driver, since the lock may also be needed by the clock driver's interrupt service routine. +PTP hardware clock requirements for '.adjphase' +----------------------------------------------- + + The 'struct ptp_clock_info' interface has a '.adjphase' function. + This function has a set of requirements from the PHC in order to be + implemented. + + * The PHC implements a servo algorithm internally that is used to + correct the offset passed in the '.adjphase' call. + * When other PTP adjustment functions are called, the PHC servo + algorithm is disabled. + + **NOTE:** '.adjphase' is not a simple time adjustment functionality + that 'jumps' the PHC clock time based on the provided offset. It + should correct the offset provided using an internal algorithm. + Supported hardware ================== diff --git a/include/linux/ptp_clock_kernel.h b/include/linux/ptp_clock_kernel.h index fdffa6a98d79..f8e8443a8b35 100644 --- a/include/linux/ptp_clock_kernel.h +++ b/include/linux/ptp_clock_kernel.h @@ -77,8 +77,10 @@ struct ptp_system_timestamp { * nominal frequency in parts per million, but with a * 16 bit binary fractional field. * - * @adjphase: Adjusts the phase offset of the hardware clock. - * parameter delta: Desired change in nanoseconds. + * @adjphase: Indicates that the PHC should use an internal servo + * algorithm to correct the provided phase offset. + * parameter delta: PHC servo phase adjustment target + * in nanoseconds. * * @adjtime: Shifts the time of the hardware clock. * parameter delta: Desired change in nanoseconds.