| Message ID | 20230719092233.137844-1-jiawenwu@trustnetic.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | c7b75bea853daeb64fc831dbf39a6bbabcc402ac |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [net,v2] net: phy: marvell10g: fix 88x3310 power up | expand |
On Wed, Jul 19, 2023 at 05:22:33PM +0800, Jiawen Wu wrote: > Clear MV_V2_PORT_CTRL_PWRDOWN bit to set power up for 88x3310 PHY, > it sometimes does not take effect immediately. And a read of this > register causes the bit not to clear. This will cause mv3310_reset() > to time out, which will fail the config initialization. So add a delay > before the next access. > > Fixes: c9cc1c815d36 ("net: phy: marvell10g: place in powersave mode at probe") > Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Thanks!
On Wed, 2023-07-19 at 17:22 +0800, Jiawen Wu wrote: > Clear MV_V2_PORT_CTRL_PWRDOWN bit to set power up for 88x3310 PHY, > it sometimes does not take effect immediately. And a read of this > register causes the bit not to clear. This will cause mv3310_reset() > to time out, which will fail the config initialization. So add a delay > before the next access. > > Fixes: c9cc1c815d36 ("net: phy: marvell10g: place in powersave mode at probe") > Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> > --- > v1 -> v2: > - change poll-bit-clear to time delay > --- > drivers/net/phy/marvell10g.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c > index 55d9d7acc32e..d4bb90d76881 100644 > --- a/drivers/net/phy/marvell10g.c > +++ b/drivers/net/phy/marvell10g.c > @@ -328,6 +328,13 @@ static int mv3310_power_up(struct phy_device *phydev) > ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, > MV_V2_PORT_CTRL_PWRDOWN); > > + /* Sometimes, the power down bit doesn't clear immediately, and > + * a read of this register causes the bit not to clear. Delay > + * 100us to allow the PHY to come out of power down mode before > + * the next access. > + */ > + udelay(100); Out of sheer ignorance, would an usleep_range(...) be more appropriate here? Thanks! Paolo
Hello: This patch was applied to netdev/net.git (main) by David S. Miller <davem@davemloft.net>: On Wed, 19 Jul 2023 17:22:33 +0800 you wrote: > Clear MV_V2_PORT_CTRL_PWRDOWN bit to set power up for 88x3310 PHY, > it sometimes does not take effect immediately. And a read of this > register causes the bit not to clear. This will cause mv3310_reset() > to time out, which will fail the config initialization. So add a delay > before the next access. > > Fixes: c9cc1c815d36 ("net: phy: marvell10g: place in powersave mode at probe") > Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> > > [...] Here is the summary with links: - [net,v2] net: phy: marvell10g: fix 88x3310 power up https://git.kernel.org/netdev/net/c/c7b75bea853d You are awesome, thank you!
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 55d9d7acc32e..d4bb90d76881 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -328,6 +328,13 @@ static int mv3310_power_up(struct phy_device *phydev) ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, MV_V2_PORT_CTRL_PWRDOWN); + /* Sometimes, the power down bit doesn't clear immediately, and + * a read of this register causes the bit not to clear. Delay + * 100us to allow the PHY to come out of power down mode before + * the next access. + */ + udelay(100); + if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || priv->firmware_ver < 0x00030000) return ret;
Clear MV_V2_PORT_CTRL_PWRDOWN bit to set power up for 88x3310 PHY, it sometimes does not take effect immediately. And a read of this register causes the bit not to clear. This will cause mv3310_reset() to time out, which will fail the config initialization. So add a delay before the next access. Fixes: c9cc1c815d36 ("net: phy: marvell10g: place in powersave mode at probe") Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> --- v1 -> v2: - change poll-bit-clear to time delay --- drivers/net/phy/marvell10g.c | 7 +++++++ 1 file changed, 7 insertions(+)