| Message ID | 20230726090909.3417030-1-haibo.chen@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2,1/3] arm64: dts: imx93: add the Flex-CAN stop mode by GPR | expand |
On 26.07.2023 17:09:07, haibo.chen@nxp.com wrote: > From: Haibo Chen <haibo.chen@nxp.com> > > imx93 A0 chip use the internal q-channel handshake signal in LPCG > and CCM to automatically handle the Flex-CAN stop mode. But this > method meet issue when do the system PM stress test. IC can't fix > it easily. So in the new imx93 A1 chip, IC drop this method, and > involve back the old way，use the GPR method to trigger the Flex-CAN > stop mode signal. Now NXP claim to drop imx93 A0, and only support > imx93 A1. So here add the stop mode through GPR. > > Signed-off-by: Haibo Chen <haibo.chen@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx93.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi > index 4ec9df78f205..d2040019e9c7 100644 > --- a/arch/arm64/boot/dts/freescale/imx93.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi > @@ -319,6 +319,7 @@ flexcan1: can@443a0000 { > assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; > assigned-clock-rates = <40000000>; > fsl,clk-source = /bits/ 8 <0>; > + fsl,stop-mode = <&anomix_ns_gpr 0x14 0>; I think there's a typo in the mainline imx93.dtsi. AFAICS it's supposed to be "aonmix_ns_gpr", not "anomix_ns_gpr". But that's a different problem to patch :) AFAICS, according to imx93, rev2 data sheet, offset 0x14 is 76.6.1.3 QCHANNEL DISABLE (QCH_DIS) and bit 0 is "GPIO1". Are you sure this is the correct reg? > status = "disabled"; > }; > > @@ -591,6 +592,7 @@ flexcan2: can@425b0000 { > assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; > assigned-clock-rates = <40000000>; > fsl,clk-source = /bits/ 8 <0>; > + fsl,stop-mode = <&wakeupmix_gpr 0x0C 2>; looks plausible, please use lower case for hex addresses. > status = "disabled"; > }; > > -- > 2.34.1 > > regards, Marc
> -----Original Message----- > From: Marc Kleine-Budde <mkl@pengutronix.de> > Sent: 2023年7月26日 17:57 > To: Bough Chen <haibo.chen@nxp.com> > Cc: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > conor+dt@kernel.org; shawnguo@kernel.org; s.hauer@pengutronix.de; > wg@grandegger.com; kernel@pengutronix.de; dl-linux-imx > <linux-imx@nxp.com>; davem@davemloft.net; edumazet@google.com; > kuba@kernel.org; pabeni@redhat.com; devicetree@vger.kernel.org; > linux-can@vger.kernel.org; netdev@vger.kernel.org > Subject: Re: [PATCH v2 1/3] arm64: dts: imx93: add the Flex-CAN stop mode by > GPR > > On 26.07.2023 17:09:07, haibo.chen@nxp.com wrote: > > From: Haibo Chen <haibo.chen@nxp.com> > > > > imx93 A0 chip use the internal q-channel handshake signal in LPCG and > > CCM to automatically handle the Flex-CAN stop mode. But this method > > meet issue when do the system PM stress test. IC can't fix it easily. > > So in the new imx93 A1 chip, IC drop this method, and involve back the > > old way，use the GPR method to trigger the Flex-CAN stop mode signal. > > Now NXP claim to drop imx93 A0, and only support > > imx93 A1. So here add the stop mode through GPR. > > > > Signed-off-by: Haibo Chen <haibo.chen@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/imx93.dtsi | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi > > b/arch/arm64/boot/dts/freescale/imx93.dtsi > > index 4ec9df78f205..d2040019e9c7 100644 > > --- a/arch/arm64/boot/dts/freescale/imx93.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi > > @@ -319,6 +319,7 @@ flexcan1: can@443a0000 { > > assigned-clock-parents = <&clk > IMX93_CLK_SYS_PLL_PFD1_DIV2>; > > assigned-clock-rates = <40000000>; > > fsl,clk-source = /bits/ 8 <0>; > > + fsl,stop-mode = <&anomix_ns_gpr 0x14 0>; > > I think there's a typo in the mainline imx93.dtsi. AFAICS it's supposed to be > "aonmix_ns_gpr", not "anomix_ns_gpr". But that's a different problem to > patch :) Yes, this is a typo. > > AFAICS, according to imx93, rev2 data sheet, offset 0x14 is 76.6.1.3 QCHANNEL > DISABLE (QCH_DIS) and bit 0 is "GPIO1". Are you sure this is the correct reg? > Imx93 A1 doc has some update, I double confirm with the internal doc and IC team, the setting is correct. I also test on imx93-9x9 qsb board, system can be wakeup by this setting. > > status = "disabled"; > > }; > > > > @@ -591,6 +592,7 @@ flexcan2: can@425b0000 { > > assigned-clock-parents = <&clk > IMX93_CLK_SYS_PLL_PFD1_DIV2>; > > assigned-clock-rates = <40000000>; > > fsl,clk-source = /bits/ 8 <0>; > > + fsl,stop-mode = <&wakeupmix_gpr 0x0C 2>; > > looks plausible, please use lower case for hex addresses. My bad, will fix. Best Regards Haibo Chen > > > status = "disabled"; > > }; > > > > -- > > 2.34.1 > > > > > > regards, > Marc > > -- > Pengutronix e.K. | Marc Kleine-Budde | > Embedded Linux | https://www.pengutronix.de | > Vertretung Nürnberg | Phone: +49-5121-206917-129 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
On 26.07.2023 11:10:10, Bough Chen wrote: > > > arch/arm64/boot/dts/freescale/imx93.dtsi | 2 ++ > > > 1 file changed, 2 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi > > > b/arch/arm64/boot/dts/freescale/imx93.dtsi > > > index 4ec9df78f205..d2040019e9c7 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx93.dtsi > > > +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi > > > @@ -319,6 +319,7 @@ flexcan1: can@443a0000 { > > > assigned-clock-parents = <&clk > > IMX93_CLK_SYS_PLL_PFD1_DIV2>; > > > assigned-clock-rates = <40000000>; > > > fsl,clk-source = /bits/ 8 <0>; > > > + fsl,stop-mode = <&anomix_ns_gpr 0x14 0>; > > > > I think there's a typo in the mainline imx93.dtsi. AFAICS it's supposed to be > > "aonmix_ns_gpr", not "anomix_ns_gpr". But that's a different problem to > > patch :) > > Yes, this is a typo. > > > > AFAICS, according to imx93, rev2 data sheet, offset 0x14 is 76.6.1.3 QCHANNEL > > DISABLE (QCH_DIS) and bit 0 is "GPIO1". Are you sure this is the correct reg? > > > > Imx93 A1 doc has some update, I double confirm with the internal doc and IC team, the setting is correct. > I also test on imx93-9x9 qsb board, system can be wakeup by this setting. Thanks for double checking. Marc
diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 4ec9df78f205..d2040019e9c7 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -319,6 +319,7 @@ flexcan1: can@443a0000 { assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; assigned-clock-rates = <40000000>; fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&anomix_ns_gpr 0x14 0>; status = "disabled"; }; @@ -591,6 +592,7 @@ flexcan2: can@425b0000 { assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; assigned-clock-rates = <40000000>; fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&wakeupmix_gpr 0x0C 2>; status = "disabled"; };