| Message ID | 20230727082550.15254-1-ante.knezic@helmholz.de (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [net-next,v4] net: dsa: mv88e6xxx: Add erratum 3.14 for 88E6390X and 88E6190X | expand |
On Thu, Jul 27, 2023 at 10:25:50AM +0200, Ante Knezic wrote: > Fixes XAUI/RXAUI lane alignment errors. > Issue causes dropped packets when trying to communicate over > fiber via SERDES lanes of port 9 and 10. > Errata document applies only to 88E6190X and 88E6390X devices. > Requires poking in undocumented registers. > > Signed-off-by: Ante Knezic <ante.knezic@helmholz.de> > --- > V4 : Rework as suggested by Vladimir Oltean <olteanv@gmail.com> > and Russell King <linux@armlinux.org.uk> > * print error in case of failure to apply erratum > * use mdiobus_c45_write instead of mdiodev_c45_write > * use bool variable instead of embedding a chip pointer inside > pcs struct. > V3 : Rework to fit the new phylink_pcs infrastructure > V2 : Rework as suggested by Andrew Lunn <andrew@lun.ch> > * make int lanes[] const > * reorder prod_nums > * update commit message to indicate we are dealing with > undocumented Marvell registers and magic values > --- > drivers/net/dsa/mv88e6xxx/pcs-639x.c | 45 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/drivers/net/dsa/mv88e6xxx/pcs-639x.c b/drivers/net/dsa/mv88e6xxx/pcs-639x.c > index 98dd49dac421..ba373656bfe1 100644 > --- a/drivers/net/dsa/mv88e6xxx/pcs-639x.c > +++ b/drivers/net/dsa/mv88e6xxx/pcs-639x.c > @@ -20,6 +20,7 @@ struct mv88e639x_pcs { > struct mdio_device mdio; > struct phylink_pcs sgmii_pcs; > struct phylink_pcs xg_pcs; > + bool erratum_3_14; > bool supports_5g; > phy_interface_t interface; > unsigned int irq; > @@ -205,13 +206,53 @@ static void mv88e639x_sgmii_pcs_pre_config(struct phylink_pcs *pcs, > mv88e639x_sgmii_pcs_control_pwr(mpcs, false); > } > > +static int mv88e6390_erratum_3_14(struct mv88e639x_pcs *mpcs) > +{ > + const int lanes[] = { MV88E6390_PORT9_LANE0, MV88E6390_PORT9_LANE1, > + MV88E6390_PORT9_LANE2, MV88E6390_PORT9_LANE3, > + MV88E6390_PORT10_LANE0, MV88E6390_PORT10_LANE1, > + MV88E6390_PORT10_LANE2, MV88E6390_PORT10_LANE3 }; > + int err, i; > + > + /* 88e6190x and 88e6390x errata 3.14: > + * After chip reset, SERDES reconfiguration or SERDES core > + * Software Reset, the SERDES lanes may not be properly aligned > + * resulting in CRC errors > + */ > + > + for (i = 0; i < ARRAY_SIZE(lanes); i++) { > + err = mdiobus_c45_write(mpcs->mdio.bus, lanes[i], > + MDIO_MMD_PHYXS, > + 0xf054, 0x400C); > + if (err) > + return err; > + > + err = mdiobus_c45_write(mpcs->mdio.bus, lanes[i], > + MDIO_MMD_PHYXS, > + 0xf054, 0x4000); > + if (err) > + return err; > + } > + > + return 0; > +} > + > static int mv88e639x_sgmii_pcs_post_config(struct phylink_pcs *pcs, > phy_interface_t interface) > { > struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs); > + int err; > > mv88e639x_sgmii_pcs_control_pwr(mpcs, true); > > + if (mpcs->erratum_3_14) { > + err = mv88e6390_erratum_3_14(mpcs); > + if (err) > + dev_err(mpcs->mdio.dev.parent, > + "failed to apply erratum 3.14: %pe\n", > + ERR_PTR(err)); > + } > + > return 0; > } > > @@ -524,6 +565,10 @@ static int mv88e6390_pcs_init(struct mv88e6xxx_chip *chip, int port) > mpcs->xg_pcs.ops = &mv88e6390_xg_pcs_ops; > mpcs->xg_pcs.neg_mode = true; > > + if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6190X || > + chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6390X) > + mpcs->erratum_3_14 = true; > + > err = mv88e639x_pcs_setup_irq(mpcs, chip, port); > if (err) > goto err_free; > -- > 2.11.0 > It's good practice that, if you had a conversation with Russell on previous versions of the patch, to keep him CCed on newer versions of it.
On Thu, 27 Jul 2023 10:25:50 +0200 Ante Knezic wrote: > Fixes XAUI/RXAUI lane alignment errors. > Issue causes dropped packets when trying to communicate over > fiber via SERDES lanes of port 9 and 10. > Errata document applies only to 88E6190X and 88E6390X devices. > Requires poking in undocumented registers. Looks like the patch was set to Changes Requested in patchwork: https://patchwork.kernel.org/project/netdevbpf/patch/20230727082550.15254-1-ante.knezic@helmholz.de/ Presumably due to lack of CC and/or Ack from Russell. Could you repost with Russell included?
diff --git a/drivers/net/dsa/mv88e6xxx/pcs-639x.c b/drivers/net/dsa/mv88e6xxx/pcs-639x.c index 98dd49dac421..ba373656bfe1 100644 --- a/drivers/net/dsa/mv88e6xxx/pcs-639x.c +++ b/drivers/net/dsa/mv88e6xxx/pcs-639x.c @@ -20,6 +20,7 @@ struct mv88e639x_pcs { struct mdio_device mdio; struct phylink_pcs sgmii_pcs; struct phylink_pcs xg_pcs; + bool erratum_3_14; bool supports_5g; phy_interface_t interface; unsigned int irq; @@ -205,13 +206,53 @@ static void mv88e639x_sgmii_pcs_pre_config(struct phylink_pcs *pcs, mv88e639x_sgmii_pcs_control_pwr(mpcs, false); } +static int mv88e6390_erratum_3_14(struct mv88e639x_pcs *mpcs) +{ + const int lanes[] = { MV88E6390_PORT9_LANE0, MV88E6390_PORT9_LANE1, + MV88E6390_PORT9_LANE2, MV88E6390_PORT9_LANE3, + MV88E6390_PORT10_LANE0, MV88E6390_PORT10_LANE1, + MV88E6390_PORT10_LANE2, MV88E6390_PORT10_LANE3 }; + int err, i; + + /* 88e6190x and 88e6390x errata 3.14: + * After chip reset, SERDES reconfiguration or SERDES core + * Software Reset, the SERDES lanes may not be properly aligned + * resulting in CRC errors + */ + + for (i = 0; i < ARRAY_SIZE(lanes); i++) { + err = mdiobus_c45_write(mpcs->mdio.bus, lanes[i], + MDIO_MMD_PHYXS, + 0xf054, 0x400C); + if (err) + return err; + + err = mdiobus_c45_write(mpcs->mdio.bus, lanes[i], + MDIO_MMD_PHYXS, + 0xf054, 0x4000); + if (err) + return err; + } + + return 0; +} + static int mv88e639x_sgmii_pcs_post_config(struct phylink_pcs *pcs, phy_interface_t interface) { struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs); + int err; mv88e639x_sgmii_pcs_control_pwr(mpcs, true); + if (mpcs->erratum_3_14) { + err = mv88e6390_erratum_3_14(mpcs); + if (err) + dev_err(mpcs->mdio.dev.parent, + "failed to apply erratum 3.14: %pe\n", + ERR_PTR(err)); + } + return 0; } @@ -524,6 +565,10 @@ static int mv88e6390_pcs_init(struct mv88e6xxx_chip *chip, int port) mpcs->xg_pcs.ops = &mv88e6390_xg_pcs_ops; mpcs->xg_pcs.neg_mode = true; + if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6190X || + chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6390X) + mpcs->erratum_3_14 = true; + err = mv88e639x_pcs_setup_irq(mpcs, chip, port); if (err) goto err_free;
Fixes XAUI/RXAUI lane alignment errors. Issue causes dropped packets when trying to communicate over fiber via SERDES lanes of port 9 and 10. Errata document applies only to 88E6190X and 88E6390X devices. Requires poking in undocumented registers. Signed-off-by: Ante Knezic <ante.knezic@helmholz.de> --- V4 : Rework as suggested by Vladimir Oltean <olteanv@gmail.com> and Russell King <linux@armlinux.org.uk> * print error in case of failure to apply erratum * use mdiobus_c45_write instead of mdiodev_c45_write * use bool variable instead of embedding a chip pointer inside pcs struct. V3 : Rework to fit the new phylink_pcs infrastructure V2 : Rework as suggested by Andrew Lunn <andrew@lun.ch> * make int lanes[] const * reorder prod_nums * update commit message to indicate we are dealing with undocumented Marvell registers and magic values --- drivers/net/dsa/mv88e6xxx/pcs-639x.c | 45 ++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+)