| Message ID | 20230807193507.6488-10-brgl@bgdev.pl (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: qcom: enable EMAC1 on sa8775p | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Not a local patch |
On Mon, Aug 07, 2023 at 09:35:07PM +0200, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Enable the second MAC on sa8775p-ride. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- > arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 74 +++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > index af50aa2d9b10..0862bfb4c580 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > @@ -356,6 +356,80 @@ queue3 { > }; > }; > > +ðernet1 { > + phy-mode = "sgmii"; > + phy-handle = <&sgmii_phy1>; This should be all you need. > + snps,shared-mdio = <&mdio0>; This is not needed, since it is implicit in the phy-handle. You need to debug why the existing -EPROBE_DEFER is not working. Andrew
On Mon, Aug 07, 2023 at 09:35:07PM +0200, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Enable the second MAC on sa8775p-ride. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- > arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 74 +++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > index af50aa2d9b10..0862bfb4c580 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > @@ -356,6 +356,80 @@ queue3 { > }; > }; > > +ðernet1 { > + phy-mode = "sgmii"; > + phy-handle = <&sgmii_phy1>; > + > + pinctrl-0 = <ðernet1_default>; > + pinctrl-names = "default"; As I stated in the earlier patch that added ethernet1_default, I don't think it makes sense. All the MDIO is happening via the pins described via ethernet0_default. > + > + snps,mtl-rx-config = <&mtl_rx_setup1>; > + snps,mtl-tx-config = <&mtl_tx_setup1>; > + snps,ps-speed = <1000>; > + snps,shared-mdio = <&mdio0>; same question as Andrew Lunn, but I'll let you respond to one of his threads. > + > + status = "okay"; > + > + mtl_rx_setup1: rx-queues-config { > + snps,rx-queues-to-use = <4>; > + snps,rx-sched-sp; > + > + queue0 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x0>; > + snps,route-up; > + snps,priority = <0x1>; > + }; > + > + queue1 { > + snps,dcb-algorithm; > + snps,map-to-dma-channel = <0x1>; > + snps,route-ptp; > + }; > + > + queue2 { > + snps,avb-algorithm; > + snps,map-to-dma-channel = <0x2>; > + snps,route-avcp; > + }; > + > + queue3 { > + snps,avb-algorithm; > + snps,map-to-dma-channel = <0x3>; > + snps,priority = <0xc>; > + }; > + }; > + > + mtl_tx_setup1: tx-queues-config { > + snps,tx-queues-to-use = <4>; > + snps,tx-sched-sp; > + > + queue0 { > + snps,dcb-algorithm; > + }; > + > + queue1 { > + snps,dcb-algorithm; > + }; > + > + queue2 { > + snps,avb-algorithm; > + snps,send_slope = <0x1000>; > + snps,idle_slope = <0x1000>; > + snps,high_credit = <0x3e800>; > + snps,low_credit = <0xffc18000>; > + }; > + > + queue3 { > + snps,avb-algorithm; > + snps,send_slope = <0x1000>; > + snps,idle_slope = <0x1000>; > + snps,high_credit = <0x3e800>; > + snps,low_credit = <0xffc18000>; > + }; > + }; > +}; > + > &i2c11 { > clock-frequency = <400000>; > pinctrl-0 = <&qup_i2c11_default>; > -- > 2.39.2 >
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index af50aa2d9b10..0862bfb4c580 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -356,6 +356,80 @@ queue3 { }; }; +ðernet1 { + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy1>; + + pinctrl-0 = <ðernet1_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + snps,ps-speed = <1000>; + snps,shared-mdio = <&mdio0>; + + status = "okay"; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + &i2c11 { clock-frequency = <400000>; pinctrl-0 = <&qup_i2c11_default>;