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Miller" , Paolo Abeni , Vadim Fedorenko , Kenneth Klette Jonassen , Rahul Rameshbabu Subject: [PATCH net] net/mlx5: Dynamic cyclecounter shift calculation for PTP free running clock Date: Mon, 21 Aug 2023 16:05:54 -0700 Message-Id: <20230821230554.236210-1-rrameshbabu@nvidia.com> X-Mailer: git-send-email 2.40.1 X-ClientProxiedBy: BYAPR11CA0073.namprd11.prod.outlook.com (2603:10b6:a03:f4::14) To BYAPR12MB2743.namprd12.prod.outlook.com (2603:10b6:a03:61::28) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BYAPR12MB2743:EE_|DM6PR12MB4909:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e6ac429-ad12-4686-a3a6-08dba29b4ef8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PWqoXL88Vvw0INPIrawClTHPs1+pwzLthkyZ2kkzigSWL5S++ek5kXNb6k9o+wg652ew4pO9vk0ESlZGB1P8vmI56wUFsTLNY0qhMW5x8TARQ9jefF/LvlVwM4Sjq5keRYmOxnWRUYFr3dJjKXMAN2jTWf1u3leETg+51S5NGAC0rQ0qPfptOOWj4pEPIlWXN1cBcjrN1NbT4oK28EWT1TczbIFGZLuyz6Yx4+E2m6aw9VWgNHJOc9Y4rfE+2Agl2ilauMKiJsfV62zsZb2edi9/ZmOM19VR0fCc2GTxzJSwTYDsHw4qmseQFmny9SwXK67pjH0jUoSeT2fqQ0MngI2m+AUYYczh3xWulPHFR66DD/Oi6JSO8MXGk1DIHrs9IGP2QCbnWZU6GhPjCW9yXMgow9iFayeyipOBsFq1EBSzoe7ARinA2rx08Do3TEfy2Xs2EsOKSHaQlCIBHZWU3XtxOuxhySD79Wp2yMnH7QwHfgGFCoPsHw8Q2bC2sZUAPTsVPLaZXM+5pfu9gYoArrAZqwtLiXhrRACZ07LjehQCAG34p6EwHr2eS8b2direhG96q3DfUSvvQfR9GU1ODI8i7jPaXW+nQGkY5Q6NTfM= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BYAPR12MB2743.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(376002)(366004)(346002)(136003)(39860400002)(396003)(451199024)(1800799009)(186009)(2906002)(83380400001)(6486002)(6506007)(38100700002)(5660300002)(26005)(86362001)(8676002)(8936002)(2616005)(107886003)(4326008)(316002)(6512007)(66476007)(54906003)(66556008)(66946007)(6916009)(966005)(478600001)(36756003)(41300700001)(1076003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0D/ObC8ze0IdbbpQ83Vzz4ft03tqZI4DqJLd9erQ456BeejYr2voC68rBvVeHJ50cCnyFFi6K5P4M+5cMM2DhEbORSd8w4ea/+EQunN+Bfl7Ez5zx3zpi8S4Z8sF3gymof/++D9kN/pPLVXRRL0MKMV/zG6XPt653vBe+7CLs6vDkpRaRUDkSjsKItC4ZV2UFomb9TRJn96kvhAjpOJ/DFtt8dwJ4nfd5GMepuZ0+sCFsIuOlbKMuIUkcAkx3AOCPIKGsvz3rAijQNPEysfWKCawLdQK+FTZ/cTDIpf/+pKubJiZXtHn/rabQlCa+FyVYHMprTNmbLNTXJia7qyifjyjP8l5qRLaMYvB4vY426j0kJbMlmrxALIvwhe4adX7gUFsDzbbCltw/b7zOOiOJc6Z6lioQQIK3Pet+7OzBnICN3jLtADwkH55/+PhfZh3aSvOpdpEXst9IqPh10MU0UWGzRF7j1Se4iw1aO9J+nN4qgwaOIetQ7rlmIyf4QPZuWjQfSQZUWpqo+eV38eEYlOlEoG3BpqpwJ5k+X1U19PC1CLGHTn7dJX4p3nWyxeBG+a/Co4Bi1DaDE6b2L8mZilhfgxN9DxkzcbM+GnVekLwW97FuCILZMYiY0Vf+QlQN3F2OVEUBA4ZKDUjLTutFJNx/fo69MoHAVyRJV4Jyla7Mc7QrvYd1gaHVKoNNaY8tj2wgR1v4astAdgVep5g1t0Lh7oNjpAPW6gRx0QV12eEQkJpjOAdIJrelWrvyaMij2nRe6Yv2tQmwd64pncupYpm/F7x3iEO0YNX6vn67sRoHSoI3+7O/oZ+4KIlkakMrNhOI2KmhdFZdWasrn/38js4Z+1qtGe56QGSSnO2iNRxKss45x69ca0jTKpWgKsnCxKTdJ/+lRkEdAUX2xlQB2PI+7Jm0sEHB5ce9cCl7ahppMisxx8SHThwGQ3ot3ndSHCCaUo28h0jqoedSVJwk1mHTUeAsDLgRfMfMS35ot+ohEMhCYGVGL4WNCe1GrkyMlrzk6KnhS0uAZuMY5HDaN8x2pid58egJDK3BhRu0yXxP8PRTUxLavAs9NKeLk1SbzWxqDQ8C7F/w+gAyO6oWIy1IXxCATIbaH310AUZ17FELC/CVtdMaDOTjgVOjElmIpPBExBPs4X78Aq06wVcBgNks4YpFcDKAK+wcDkxX+e1tC0qPkX8KTZUa1bWoEJyIyuRgWo3MOzmDhTGbQsWL9L9TR78CPYtcOtI0t+UIV7hUFNn0sx3meGlarS8KyYxVvkss6IVw9IYzp8FZSQ+XqXCRv+5QOEwFSnDPf8TJhdK9jaP4FYHPtoN3isXaqAaQI523PGRjuDFXj4ozi5MbU+ru5yW1ffKoiy4sSeBQZDExhRfPxXFiEHUblt11He2zMaljLKU/ZFlYSwcrTSi0w91LBJvP5iSiM8/bhdT+eG0xGyLzRaC+Pkog98o5UzcfB/WTI8DC3++25YqaVLoBAOUxlfd3gSVqJhwzYZEFW18y7CvSX/lDWhsuT0RHDHOcKHwuesZKlmHhQu0iZozH6tKEMjSDGt8zjb4o67FtYDti9oP6cIIt6Zlu5IlmLyX4RyETPVApAVT7eWTyrw48Q== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2e6ac429-ad12-4686-a3a6-08dba29b4ef8 X-MS-Exchange-CrossTenant-AuthSource: BYAPR12MB2743.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Aug 2023 23:06:53.3026 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: pIRC3drCOpZl0Jp2wIYolwJ00seBjJWgLPLmzWQVbxwcgKvOeie/CmUvQYUSn/Rt0qQx9i97gxXAxipEULQQsA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4909 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Use a dynamic calculation to determine the shift value for the internal timer cyclecounter that will lead to the highest precision frequency adjustments. Previously used a constant for the shift value assuming all devices supported by the driver had a nominal frequency of 1GHz. However, there are devices that operate at different frequencies. The previous shift value constant would break the PHC functionality for those devices. Reported-by: Vadim Fedorenko Closes: https://lore.kernel.org/netdev/20230815151507.3028503-1-vadfed@meta.com/ Fixes: 6a4010927562 ("net/mlx5: Update cyclecounter shift value to improve ptp free running mode precision") Signed-off-by: Rahul Rameshbabu Tested-by: Vadim Fedorenko Reviewed-by: Jacob Keller Reviewed-by: Simon Horman Acked-by: Saeed Mahameed --- Notes: Devices tested on: * ConnectX 4 * ConnectX 4-Lx * ConnectX 5 * ConnectX 6 * ConnectX 6-Dx * ConnectX 7 .../ethernet/mellanox/mlx5/core/lib/clock.c | 32 ++++++++++++++++--- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index 377372f0578a..aa29f09e8356 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -32,16 +32,13 @@ #include #include +#include #include #include #include "lib/eq.h" #include "en.h" #include "clock.h" -enum { - MLX5_CYCLES_SHIFT = 31 -}; - enum { MLX5_PIN_MODE_IN = 0x0, MLX5_PIN_MODE_OUT = 0x1, @@ -93,6 +90,31 @@ static bool mlx5_modify_mtutc_allowed(struct mlx5_core_dev *mdev) return MLX5_CAP_MCAM_FEATURE(mdev, ptpcyc2realtime_modify); } +static u32 mlx5_ptp_shift_constant(u32 dev_freq_khz) +{ + /* Optimal shift constant leads to corrections above just 1 scaled ppm. + * + * Two sets of equations are needed to derive the optimal shift + * constant for the cyclecounter. + * + * dev_freq_khz * 1000 / 2^shift_constant = 1 scaled_ppm + * ppb = scaled_ppm * 1000 / 2^16 + * + * Using the two equations together + * + * dev_freq_khz * 1000 / 1 scaled_ppm = 2^shift_constant + * dev_freq_khz * 2^16 / 1 ppb = 2^shift_constant + * dev_freq_khz = 2^(shift_constant - 16) + * + * then yields + * + * shift_constant = ilog2(dev_freq_khz) + 16 + */ + + return min(ilog2(dev_freq_khz) + 16, + ilog2((U32_MAX / NSEC_PER_MSEC) * dev_freq_khz)); +} + static s32 mlx5_ptp_getmaxphase(struct ptp_clock_info *ptp) { struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); @@ -909,7 +931,7 @@ static void mlx5_timecounter_init(struct mlx5_core_dev *mdev) dev_freq = MLX5_CAP_GEN(mdev, device_frequency_khz); timer->cycles.read = read_internal_timer; - timer->cycles.shift = MLX5_CYCLES_SHIFT; + timer->cycles.shift = mlx5_ptp_shift_constant(dev_freq); timer->cycles.mult = clocksource_khz2mult(dev_freq, timer->cycles.shift); timer->nominal_c_mult = timer->cycles.mult;