Message ID | 20230824095001.3408573-5-pulehui@huaweicloud.com (mailing list archive) |
---|---|
State | Accepted |
Commit | d9839f16c1502556993552746452c862cb1c41af |
Delegated to: | BPF |
Headers | show |
Series | Add support cpu v4 insns for RV64 | expand |
diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c index bcf1e7509cb9..076619f4aa82 100644 --- a/arch/riscv/net/bpf_jit_comp64.c +++ b/arch/riscv/net/bpf_jit_comp64.c @@ -1327,7 +1327,11 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, /* JUMP off */ case BPF_JMP | BPF_JA: - rvoff = rv_offset(i, off, ctx); + case BPF_JMP32 | BPF_JA: + if (BPF_CLASS(code) == BPF_JMP) + rvoff = rv_offset(i, off, ctx); + else + rvoff = rv_offset(i, imm, ctx); ret = emit_jump_and_link(RV_REG_ZERO, rvoff, true, ctx); if (ret) return ret;