| Message ID | 20230919035839.3297328-5-pulehui@huaweicloud.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | BPF |
| Headers | show |
| Series | Zbb support and code simplification for RV64 JIT | expand |
On Tue, Sep 19, 2023 at 11:58:37AM +0800, Pu Lehui wrote: > From: Pu Lehui <pulehui@huawei.com> > > Add necessary Zbb instructions introduced by [0] to reduce code size and > improve performance of RV64 JIT. Meanwhile, a runtime deteted helper is > added to check whether the CPU supports Zbb instructions. > > Link: https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf [0] > Suggested-by: Conor Dooley <conor@kernel.org> Nah, you can drop this. It was just a review comment :) > Signed-off-by: Pu Lehui <pulehui@huawei.com> > --- > arch/riscv/net/bpf_jit.h | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h > index 8e0ef4d08..4e24fb2bd 100644 > --- a/arch/riscv/net/bpf_jit.h > +++ b/arch/riscv/net/bpf_jit.h > @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void) > return IS_ENABLED(CONFIG_RISCV_ISA_C); > } > > +static inline bool rvzbb_enabled(void) > +{ > + return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); This looks like it should work, thanks for changing it. Cheers, Conor.
On 2023/9/19 15:38, Conor Dooley wrote: > On Tue, Sep 19, 2023 at 11:58:37AM +0800, Pu Lehui wrote: >> From: Pu Lehui <pulehui@huawei.com> >> >> Add necessary Zbb instructions introduced by [0] to reduce code size and >> improve performance of RV64 JIT. Meanwhile, a runtime deteted helper is >> added to check whether the CPU supports Zbb instructions. >> >> Link: https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf [0] >> Suggested-by: Conor Dooley <conor@kernel.org> > > Nah, you can drop this. It was just a review comment :) > OK, will drop if have next >> Signed-off-by: Pu Lehui <pulehui@huawei.com> >> --- >> arch/riscv/net/bpf_jit.h | 26 ++++++++++++++++++++++++++ >> 1 file changed, 26 insertions(+) >> >> diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h >> index 8e0ef4d08..4e24fb2bd 100644 >> --- a/arch/riscv/net/bpf_jit.h >> +++ b/arch/riscv/net/bpf_jit.h >> @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void) >> return IS_ENABLED(CONFIG_RISCV_ISA_C); >> } >> >> +static inline bool rvzbb_enabled(void) >> +{ >> + return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); > > This looks like it should work, thanks for changing it. > > Cheers, > Conor.
Pu Lehui <pulehui@huaweicloud.com> writes: > From: Pu Lehui <pulehui@huawei.com> > > Add necessary Zbb instructions introduced by [0] to reduce code size and > improve performance of RV64 JIT. Meanwhile, a runtime deteted helper is > added to check whether the CPU supports Zbb instructions. > > Link: https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf [0] > Suggested-by: Conor Dooley <conor@kernel.org> > Signed-off-by: Pu Lehui <pulehui@huawei.com> > --- > arch/riscv/net/bpf_jit.h | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h > index 8e0ef4d08..4e24fb2bd 100644 > --- a/arch/riscv/net/bpf_jit.h > +++ b/arch/riscv/net/bpf_jit.h > @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void) > return IS_ENABLED(CONFIG_RISCV_ISA_C); > } > > +static inline bool rvzbb_enabled(void) > +{ > + return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); > +} > + > enum { > RV_REG_ZERO = 0, /* The constant value 0 */ > RV_REG_RA = 1, /* Return address */ > @@ -727,6 +732,27 @@ static inline u16 rvc_swsp(u32 imm8, u8 rs2) > return rv_css_insn(0x6, imm, rs2, 0x2); > } > > +/* RVZBB instrutions. */ > +static inline u32 rvzbb_sextb(u8 rd, u8 rs1) > +{ > + return rv_i_insn(0x604, rs1, 1, rd, 0x13); > +} > + > +static inline u32 rvzbb_sexth(u8 rd, u8 rs1) > +{ > + return rv_i_insn(0x605, rs1, 1, rd, 0x13); > +} > + > +static inline u32 rvzbb_zexth(u8 rd, u8 rs) > +{ > + return rv_i_insn(0x80, rs, 4, rd, __riscv_xlen == 64 ? 0x3b : 0x33); Encoding funcs are hard to read as it is, so let's try to be a bit more explicit. I would prefer a | if (IS_ENABLED(CONFIG_64BIT)) | return 64bitvariant | return 32bitvariant version. Or a 64-bit only variant elsewhere, since this series is only aimed for 64-bit anyway. > +} > + > +static inline u32 rvzbb_rev8(u8 rd, u8 rs) > +{ > + return rv_i_insn(__riscv_xlen == 64 ? 0x6b8 : 0x698, rs, 5, rd, 0x13); Dito. Björn
diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h index 8e0ef4d08..4e24fb2bd 100644 --- a/arch/riscv/net/bpf_jit.h +++ b/arch/riscv/net/bpf_jit.h @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void) return IS_ENABLED(CONFIG_RISCV_ISA_C); } +static inline bool rvzbb_enabled(void) +{ + return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); +} + enum { RV_REG_ZERO = 0, /* The constant value 0 */ RV_REG_RA = 1, /* Return address */ @@ -727,6 +732,27 @@ static inline u16 rvc_swsp(u32 imm8, u8 rs2) return rv_css_insn(0x6, imm, rs2, 0x2); } +/* RVZBB instrutions. */ +static inline u32 rvzbb_sextb(u8 rd, u8 rs1) +{ + return rv_i_insn(0x604, rs1, 1, rd, 0x13); +} + +static inline u32 rvzbb_sexth(u8 rd, u8 rs1) +{ + return rv_i_insn(0x605, rs1, 1, rd, 0x13); +} + +static inline u32 rvzbb_zexth(u8 rd, u8 rs) +{ + return rv_i_insn(0x80, rs, 4, rd, __riscv_xlen == 64 ? 0x3b : 0x33); +} + +static inline u32 rvzbb_rev8(u8 rd, u8 rs) +{ + return rv_i_insn(__riscv_xlen == 64 ? 0x6b8 : 0x698, rs, 5, rd, 0x13); +} + /* * RV64-only instructions. *