| Message ID | 20230919035839.3297328-6-pulehui@huaweicloud.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | BPF |
| Headers | show |
| Series | Zbb support and code simplification for RV64 JIT | expand |
Pu Lehui <pulehui@huaweicloud.com> writes: > From: Pu Lehui <pulehui@huawei.com> > > Add 8-bit and 16-bit sign-extention wraper with Zbb support to optimize > sign-extension mov instructions. > > Signed-off-by: Pu Lehui <pulehui@huawei.com> > --- > arch/riscv/net/bpf_jit.h | 20 ++++++++++++++++++++ > arch/riscv/net/bpf_jit_comp64.c | 5 +++-- > 2 files changed, 23 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h > index 4e24fb2bd..944bdd6e4 100644 > --- a/arch/riscv/net/bpf_jit.h > +++ b/arch/riscv/net/bpf_jit.h > @@ -1110,6 +1110,26 @@ static inline void emit_subw(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx) > emit(rv_subw(rd, rs1, rs2), ctx); > } > > +static inline void emit_sextb(u8 rd, u8 rs, struct rv_jit_context *ctx) > +{ > + if (rvzbb_enabled()) { > + emit(rvzbb_sextb(rd, rs), ctx); > + } else { > + emit_slli(rd, rs, 56, ctx); > + emit_srai(rd, rd, 56, ctx); > + } > +} > + > +static inline void emit_sexth(u8 rd, u8 rs, struct rv_jit_context *ctx) > +{ > + if (rvzbb_enabled()) { > + emit(rvzbb_sexth(rd, rs), ctx); > + } else { > + emit_slli(rd, rs, 48, ctx); > + emit_srai(rd, rd, 48, ctx); > + } > +} Nit/personal style: I really find it easier to read early-exit code, than nested if-else. | if (cond) { | foo(); | return; | } | | bar(); > + > static inline void emit_sextw(u8 rd, u8 rs, struct rv_jit_context *ctx) > { > emit_addiw(rd, rs, 0, ctx); > diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c > index 0c6ffe11a..f4ca6b787 100644 > --- a/arch/riscv/net/bpf_jit_comp64.c > +++ b/arch/riscv/net/bpf_jit_comp64.c > @@ -1027,9 +1027,10 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, > emit_mv(rd, rs, ctx); > break; > case 8: > + emit_sextb(rd, rs, ctx); > + break; > case 16: > - emit_slli(RV_REG_T1, rs, 64 - insn->off, ctx); > - emit_srai(rd, RV_REG_T1, 64 - insn->off, ctx); > + emit_sexth(rd, rs, ctx); Acked-by: Björn Töpel <bjorn@kernel.org>
diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h index 4e24fb2bd..944bdd6e4 100644 --- a/arch/riscv/net/bpf_jit.h +++ b/arch/riscv/net/bpf_jit.h @@ -1110,6 +1110,26 @@ static inline void emit_subw(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx) emit(rv_subw(rd, rs1, rs2), ctx); } +static inline void emit_sextb(u8 rd, u8 rs, struct rv_jit_context *ctx) +{ + if (rvzbb_enabled()) { + emit(rvzbb_sextb(rd, rs), ctx); + } else { + emit_slli(rd, rs, 56, ctx); + emit_srai(rd, rd, 56, ctx); + } +} + +static inline void emit_sexth(u8 rd, u8 rs, struct rv_jit_context *ctx) +{ + if (rvzbb_enabled()) { + emit(rvzbb_sexth(rd, rs), ctx); + } else { + emit_slli(rd, rs, 48, ctx); + emit_srai(rd, rd, 48, ctx); + } +} + static inline void emit_sextw(u8 rd, u8 rs, struct rv_jit_context *ctx) { emit_addiw(rd, rs, 0, ctx); diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c index 0c6ffe11a..f4ca6b787 100644 --- a/arch/riscv/net/bpf_jit_comp64.c +++ b/arch/riscv/net/bpf_jit_comp64.c @@ -1027,9 +1027,10 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, emit_mv(rd, rs, ctx); break; case 8: + emit_sextb(rd, rs, ctx); + break; case 16: - emit_slli(RV_REG_T1, rs, 64 - insn->off, ctx); - emit_srai(rd, RV_REG_T1, 64 - insn->off, ctx); + emit_sexth(rd, rs, ctx); break; case 32: emit_sextw(rd, rs, ctx);