@@ -271,10 +271,33 @@ int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);
bool ice_is_pca9575_present(struct ice_hw *hw);
+
+#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
+
bool ice_is_phy_rclk_present(struct ice_hw *hw);
bool ice_is_clock_mux_present_e810t(struct ice_hw *hw);
-int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx);
bool ice_is_cgu_present(struct ice_hw *hw);
+
+#else /* !CONFIG_PTP_1588_CLOCK */
+
+static inline bool ice_is_phy_rclk_present(const struct ice_hw *hw)
+{
+ return false;
+}
+
+static inline bool ice_is_clock_mux_present_e810t(const struct ice_hw *hw)
+{
+ return false;
+}
+
+static inline bool ice_is_cgu_present(const struct ice_hw *hw)
+{
+ return false;
+}
+
+#endif /* !CONFIG_PTP_1588_CLOCK */
+
+int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx);
enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input);
struct dpll_pin_frequency *
ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num);
Starting the cited commit, ice_lib.c unconditionally refers to three functions compiled only when CONFIG_PTP_1588_CLOCK is set (as they're located in ice_ptp_hw.c): ERROR: modpost: "ice_is_clock_mux_present_e810t" [drivers/net/ethernet/intel/ice/ice.ko] undefined! ERROR: modpost: "ice_is_phy_rclk_present" [drivers/net/ethernet/intel/ice/ice.ko] undefined! ERROR: modpost: "ice_is_cgu_present" [drivers/net/ethernet/intel/ice/ice.ko] undefined! These three are HW feature tests and it is safe to stub them as `return false` when PTP support is disabled. Fixes: 8a3a565ff210 ("ice: add admin commands to access cgu configuration") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202309181001.G72eBLpj-lkp@intel.com Signed-off-by: Alexander Lobakin <aleksander.lobakin@intel.com> --- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 25 ++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)