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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044F7.mail.protection.outlook.com (10.167.241.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6933.4 via Frontend Transport; Wed, 18 Oct 2023 14:46:17 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 18 Oct 2023 09:46:14 -0500 From: Raju Rangoju To: CC: , , , , , Raju Rangoju , Sudheesh Mavila Subject: [PATCH net-next 2/2] amd-xgbe: Add support for AMD Crater ethernet device Date: Wed, 18 Oct 2023 20:14:50 +0530 Message-ID: <20231018144450.2061125-3-Raju.Rangoju@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231018144450.2061125-1-Raju.Rangoju@amd.com> References: <20231018144450.2061125-1-Raju.Rangoju@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F7:EE_|DM6PR12MB5023:EE_ X-MS-Office365-Filtering-Correlation-Id: 9ed4f338-99be-47e9-b082-08dbcfe8fca5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Oct 2023 14:46:17.9417 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ed4f338-99be-47e9-b082-08dbcfe8fca5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB5023 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org The AMD Crater device has new window settings for the XPCS access, add support to adopt to the new window settings. There is a hardware bug where in the BAR1 registers cannot be accessed directly. As a fallback mechanism, access these PCS registers through indirect access via SMN. Co-developed-by: Sudheesh Mavila Signed-off-by: Sudheesh Mavila Acked-by: Shyam Sundar S K Signed-off-by: Raju Rangoju --- drivers/net/ethernet/amd/xgbe/xgbe-common.h | 5 ++++ drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 33 +++++++++++++++++---- drivers/net/ethernet/amd/xgbe/xgbe-pci.c | 32 +++++++++++++++----- drivers/net/ethernet/amd/xgbe/xgbe.h | 6 ++++ 4 files changed, 63 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h index 3b70f6737633..e1f70f0528ef 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h +++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h @@ -900,6 +900,11 @@ #define PCS_V2_RV_WINDOW_SELECT 0x1064 #define PCS_V2_YC_WINDOW_DEF 0x18060 #define PCS_V2_YC_WINDOW_SELECT 0x18064 +#define PCS_V2_RN_WINDOW_DEF 0xF8078 +#define PCS_V2_RN_WINDOW_SELECT 0xF807c + +#define PCS_RN_SMN_BASE_ADDR 0x11E00000 +#define PCS_RN_PORT_ADDR_SIZE 0x100000 /* PCS register entry bit positions and sizes */ #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6 diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c index f393228d41c7..da8ec218282f 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c @@ -1176,8 +1176,17 @@ static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); spin_lock_irqsave(&pdata->xpcs_lock, flags); - XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); - mmd_data = XPCS16_IOREAD(pdata, offset); + if (pdata->vdata->is_crater) { + amd_smn_write(0, + (pdata->xphy_base + pdata->xpcs_window_sel_reg), + index); + amd_smn_read(0, pdata->xphy_base + offset, &mmd_data); + mmd_data = (offset % ALIGNMENT_VAL) ? + ((mmd_data >> 16) & 0xffff) : (mmd_data & 0xffff); + } else { + XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); + mmd_data = XPCS16_IOREAD(pdata, offset); + } spin_unlock_irqrestore(&pdata->xpcs_lock, flags); return mmd_data; @@ -1186,8 +1195,8 @@ static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, int mmd_reg, int mmd_data) { + unsigned int mmd_address, index, offset, crtr_mmd_data; unsigned long flags; - unsigned int mmd_address, index, offset; if (mmd_reg & XGBE_ADDR_C45) mmd_address = mmd_reg & ~XGBE_ADDR_C45; @@ -1208,8 +1217,22 @@ static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); spin_lock_irqsave(&pdata->xpcs_lock, flags); - XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); - XPCS16_IOWRITE(pdata, offset, mmd_data); + if (pdata->vdata->is_crater) { + amd_smn_write(0, (pdata->xphy_base + pdata->xpcs_window_sel_reg), index); + amd_smn_read(0, pdata->xphy_base + offset, &crtr_mmd_data); + if (offset % ALIGNMENT_VAL) { + crtr_mmd_data &= ~GENMASK(31, 16); + crtr_mmd_data |= (mmd_data << 16); + } else { + crtr_mmd_data &= ~GENMASK(15, 0); + crtr_mmd_data |= (mmd_data); + } + amd_smn_write(0, (pdata->xphy_base + pdata->xpcs_window_sel_reg), index); + amd_smn_write(0, (pdata->xphy_base + offset), crtr_mmd_data); + } else { + XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); + XPCS16_IOWRITE(pdata, offset, mmd_data); + } spin_unlock_irqrestore(&pdata->xpcs_lock, flags); } diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c index a17359d43b45..90ad520d3c29 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c @@ -279,15 +279,21 @@ static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF; pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT; } else if (rdev && (rdev->vendor == PCI_VENDOR_ID_AMD) && - (rdev->device == 0x14b5)) { - pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF; - pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT; - - /* Yellow Carp devices do not need cdr workaround */ + ((rdev->device == 0x14b5) || (rdev->device == 0x1630))) { + /* Yellow Carp and Crater devices + * do not need cdr workaround and RRC + */ pdata->vdata->an_cdr_workaround = 0; - - /* Yellow Carp devices do not need rrc */ pdata->vdata->enable_rrc = 0; + + if (rdev->device == 0x1630) { + pdata->xpcs_window_def_reg = PCS_V2_RN_WINDOW_DEF; + pdata->xpcs_window_sel_reg = PCS_V2_RN_WINDOW_SELECT; + pdata->vdata->is_crater = true; + } else { + pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF; + pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT; + } } else { pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; @@ -295,7 +301,17 @@ static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) pci_dev_put(rdev); /* Configure the PCS indirect addressing support */ - reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); + if (pdata->vdata->is_crater) { + reg = XP_IOREAD(pdata, XP_PROP_0); + pdata->xphy_base = PCS_RN_SMN_BASE_ADDR + + (PCS_RN_PORT_ADDR_SIZE * + XP_GET_BITS(reg, XP_PROP_0, PORT_ID)); + if (netif_msg_probe(pdata)) + dev_dbg(dev, "xphy_base = %#08x\n", pdata->xphy_base); + amd_smn_read(0, pdata->xphy_base + (pdata->xpcs_window_def_reg), ®); + } else { + reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); + } pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); pdata->xpcs_window <<= 6; pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h index ad136ed493ed..a161fac35643 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe.h +++ b/drivers/net/ethernet/amd/xgbe/xgbe.h @@ -133,6 +133,7 @@ #include #include #include +#include #define XGBE_DRV_NAME "amd-xgbe" #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" @@ -305,6 +306,9 @@ /* MDIO port types */ #define XGMAC_MAX_C22_PORT 3 + /* offset alignment */ +#define ALIGNMENT_VAL 4 + /* Link mode bit operations */ #define XGBE_ZERO_SUP(_ls) \ ethtool_link_ksettings_zero_link_mode((_ls), supported) @@ -1046,6 +1050,7 @@ struct xgbe_version_data { unsigned int rx_desc_prefetch; unsigned int an_cdr_workaround; unsigned int enable_rrc; + bool is_crater; }; struct xgbe_prv_data { @@ -1056,6 +1061,7 @@ struct xgbe_prv_data { struct device *dev; struct platform_device *phy_platdev; struct device *phy_dev; + unsigned int xphy_base; /* Version related data */ struct xgbe_version_data *vdata;