From patchwork Tue Nov 14 10:55:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Gantois X-Patchwork-Id: 13455138 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB57A224CD; Tue, 14 Nov 2023 10:56:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="b6Bj/h2X" Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30BC3D55; Tue, 14 Nov 2023 02:56:06 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id CFEAA2000C; Tue, 14 Nov 2023 10:56:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1699959364; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tZKAGIL7tCosSaUSk8d96o5LmNKTOtXF6OZIhSqTXQM=; b=b6Bj/h2XqPg58e03lV7lvnuIUso2Fk7mPeo/2rsceinq5EroVHSLt9pk1HF2/fwdms1i5M ZFluwKh2qScGS14WUIkO45EU3B+KGp13zKru3018wcB+xJqFVVR34a5ZdKzXnJ9AgQtxOw teKb7aegdaUGaWmiB5LtEGGIFNDlDAIzvKkHAtEYwkYznD3q7Iuke2ivfF/IokDJE2Nl0g 7P766aIET6JaJ4Ua+m1fKzeqJ2PxmlGut6Skm26PuxOk30cHb8PRmHiw7nsVcw2NKfLfrJ qUoNS7cQQXSCGCkeJG652aeLrON4QzQV6dKVY300HjPhCwT+HUheqAvZ7ZvavA== From: Romain Gantois To: davem@davemloft.net, Rob Herring , Krzysztof Kozlowski Cc: Romain Gantois , Jakub Kicinski , Eric Dumazet , Paolo Abeni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, thomas.petazzoni@bootlin.com, Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Vladimir Oltean , Luka Perkov , Robert Marko , Andy Gross , Bjorn Andersson , Konrad Dybcio Subject: [PATCH net-next v3 8/8] ARM: dts: qcom: ipq4019: Add description for the IPQ4019 ESS EDMA and switch Date: Tue, 14 Nov 2023 11:55:58 +0100 Message-ID: <20231114105600.1012056-9-romain.gantois@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114105600.1012056-1-romain.gantois@bootlin.com> References: <20231114105600.1012056-1-romain.gantois@bootlin.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: romain.gantois@bootlin.com X-Patchwork-Delegate: kuba@kernel.org The Qualcomm IPQ4019 includes a modified version of the QCA8K Ethernet switch. The switch's CPU port is connected to the SoC through the internal EDMA Ethernet controller. Add support for these two devices, which are coupled tightly enough to justify treating them as a single device. Signed-off-by: Romain Gantois --- .../boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi | 13 +++ arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 94 +++++++++++++++++++ 2 files changed, 107 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi index da67d55fa557..6a185b8b31c6 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi @@ -242,6 +242,19 @@ &mdio { pinctrl-names = "default"; }; +&switch { + status = "okay"; +}; + +&swport4 { + status = "okay"; + label = "lan"; +}; + +&swport5 { + status = "okay"; +}; + &wifi0 { status = "okay"; nvmem-cell-names = "pre-calibration"; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 9844e0b7cff9..5a4e5d408f72 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -596,6 +596,100 @@ wifi1: wifi@a800000 { status = "disabled"; }; + switch: switch@c000000 { + compatible = "qcom,ipq4019-ess"; + reg = <0xc000000 0x80000>, <0x98000 0x800>, <0xc080000 0x8000>; + reg-names = "base", "psgmii_phy", "edma"; + resets = <&gcc ESS_PSGMII_ARES>, <&gcc ESS_RESET>; + reset-names = "psgmii", "ess"; + clocks = <&gcc GCC_ESS_CLK>; + clock-names = "ess"; + mdio = <&mdio>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + swport1: port@1 { /* MAC1 */ + reg = <1>; + label = "lan1"; + phy-handle = <ðphy0>; + phy-mode = "psgmii"; + + status = "disabled"; + }; + + swport2: port@2 { /* MAC2 */ + reg = <2>; + label = "lan2"; + phy-handle = <ðphy1>; + phy-mode = "psgmii"; + + status = "disabled"; + }; + + swport3: port@3 { /* MAC3 */ + reg = <3>; + label = "lan3"; + phy-handle = <ðphy2>; + phy-mode = "psgmii"; + + status = "disabled"; + }; + + swport4: port@4 { /* MAC4 */ + reg = <4>; + label = "lan4"; + phy-handle = <ðphy3>; + phy-mode = "psgmii"; + + status = "disabled"; + }; + + swport5: port@5 { /* MAC5 */ + reg = <5>; + label = "wan"; + phy-handle = <ðphy4>; + phy-mode = "psgmii"; + + status = "disabled"; + }; + }; + }; + mdio: mdio@90000 { #address-cells = <1>; #size-cells = <0>;