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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QHB8yg1XhySAw0/NiaJiEjXS5AriutNqn8DGDvLuaBEKbaLt8K0f64GyMEuGnYsiNTZA6TmgjSvKU7ZACjtrh972gaFMXI5cx2B04Q45SvRjxjCGF2aso9hA1deFbeHUwZomwPORUf1ouZJARlQ6++I704OOxrIoxbFFKUKpby8WsNBq0J3Kse2uctm28IgwIO92IMDILMM4wUaff/wMqXgqA+GXmbLa/uZrR7Cxl/8SWeRUyiZRzQ3wUooQ1VHjUEgRnmjSCzGoeWygcJ6W4uNh7Ri3TmYYsRi1NFjK741GUg7IKHd5FSnVDVLulCmdXkBuYyxAoDbg0e9pxd8rzCJigWQjYmcmpKmjxLQ5x41gPGGPTgfOdvVcL5ojC6xwx7bGBA423EkslWIDB6WrB9sOEYnCP5T/OLCR4avgYTQGRa+IFQxUVGza8jj6E5kqxXVKiVersHlCO9o0DvpnBp040BrHZ2iIHzLIOP+DSgT5gEVWep16Qi1R8kMOf7lLRZgz7e2RcG0C3BQOi+0ZN9jT/SXelDTWmjHtKqetapTIh21utl7VxtOkaFMwj2DSRLoOKTK6yKpHNw7h+g8/e/ZO4ZsOvLWLVINdygtV+Rj7hfxgeoWJher7p6o9P02iIrRKKM4z6NHaRedUzJqGWWObxwUNXM4yCEg2sAVKIfBJCSgY/d9Er/DsneLDr/fm0t6YgxWr1zELW5j/10xNJid2LJMXxcbuGJpa0eAMk6/8YbsUR6iDot4Hxl/MJPALj3jQTUetSAbohUSko0vYMX8VVlPk4ay9uqMLrTqO2sDwm36hkvnn5mvGlUNMuTF+zCZ5SgcjA/DeX+qwYeGZGZuTqoheNsTCAwHQ+YAxhF72FaIM0+38B4gYgltxIbDPiOyBeOfWQgfhkMYQEj3GfFmsmG+EFPC0K7Ez3JWpf72OO9PzzISs14r/Qod0cJqlATcaIiSRm9XyULYiB5/ShyDS3M72qS0NReTvdNKqCoQh1xmw4YFl1IiVgk0vDrlLRDys8Lc+FstVId69rRURL4F4FYDC3vU4tCBEPtyJ7RtzCSgRmKl35HITCd7G1VAvKFO9jXPCA1n+tVOS9ts6lPT1EOj/ITFidX1c8DzNHgg9MmADj7ZB9H2ngLT/zrnwnyvsJ5um9HHzPX6Uya1GWlbGrZnXtcSKn+x64cu/qS5hSlEb3qVZJ9BibBxLY0l4mq+Atf1rqsxvS9mNNXvkiGWlWW7A7hyxhEzs+ar5MEXaA0txVIQjVfbBWl0KEt5lcmXNbQBev15485tLeHva5O2U7gkbReZ8ojk5DZjA0YrHOA7lSt1pkVCGvJTjiZodqN0ZEh04nmKIhlxZp+EK5ywd4+Q5Cp/KHvMDEUSRJ6aiodwgBYA9H5dfcH7OY0pmltcKb00HaGaa6gRvis0apQC3SxqBPDZLmzcyQV2DwJZeNixGC+ljh/JXxSksAP+gsBHyKTy5TnuW1jPI5Jz5VpDVN4ulWOomkBnW+QwDCvMLo3YqB9aVvs+81ZSKrGE+9c5xNn4PM4zlUnrtaoVRZzPNtloL3t9+IoJaxvu05LdD4K7HHoVTByZSS/ZlYGj2 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 794980a6-1c9b-42e4-5330-08dbeb61dc0e X-MS-Exchange-CrossTenant-AuthSource: SJ1PR12MB6075.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Nov 2023 13:49:34.1189 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: SCoAVhvUO/9JnQowjz12kjLOVQPS9jzswI93VvOge5OkkoM9qg9pV5XRURBRJ3RqKQqsiN9w9whaORgUqt4JkA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5800 X-Patchwork-Delegate: kuba@kernel.org From: Or Gerlitz The mlx5e driver uses ICO SQs for internal control operations which are not visible to the network stack, such as UMR mapping for striding RQ (MPWQ) and etc more cases. The upcoming nvmeotcp offload uses ico sq for umr mapping as part of the offload. As a pre-step for nvmeotcp ico sqs which have their own napi and need to comply with budget, add the budget as parameter to the polling of cqs related to ico sqs. The polling already stops after a limit is reached, so just have the caller to provide this limit as the budget. Additionnaly, we move the mdev pointer directly on the icosq structure. This provides better separation between channels to ICO SQs for use-cases where they are not tightly coupled (such as the upcoming nvmeotcp code). No functional change here. Signed-off-by: Or Gerlitz Signed-off-by: Aurelien Aptel Reviewed-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c | 4 ++-- drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h | 2 +- drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c | 2 +- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 5 ++--- drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 4 ++-- drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c | 4 ++-- 7 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index b2a5da9739d2..1e1d8f3d2b24 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -555,6 +555,7 @@ struct mlx5e_icosq { /* control path */ struct mlx5_wq_ctrl wq_ctrl; struct mlx5e_channel *channel; + struct mlx5_core_dev *mdev; struct work_struct recover_work; } ____cacheline_aligned_in_smp; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c index 4358798d6ce1..9cde6ce17992 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c @@ -46,7 +46,7 @@ static int mlx5e_query_rq_state(struct mlx5_core_dev *dev, u32 rqn, u8 *state) static int mlx5e_wait_for_icosq_flush(struct mlx5e_icosq *icosq) { - struct mlx5_core_dev *dev = icosq->channel->mdev; + struct mlx5_core_dev *dev = icosq->mdev; unsigned long exp_time; exp_time = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, FLUSH_ON_ERROR)); @@ -91,7 +91,7 @@ static int mlx5e_rx_reporter_err_icosq_cqe_recover(void *ctx) rq = &icosq->channel->rq; if (test_bit(MLX5E_RQ_STATE_ENABLED, &icosq->channel->xskrq.state)) xskrq = &icosq->channel->xskrq; - mdev = icosq->channel->mdev; + mdev = icosq->mdev; dev = icosq->channel->netdev; err = mlx5_core_query_sq_state(mdev, icosq->sqn, &state); if (err) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h index 879d698b6119..cdd7fbf218ae 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h @@ -62,7 +62,7 @@ void mlx5e_trigger_irq(struct mlx5e_icosq *sq); void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe); void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); int mlx5e_napi_poll(struct napi_struct *napi, int budget); -int mlx5e_poll_ico_cq(struct mlx5e_cq *cq); +int mlx5e_poll_ico_cq(struct mlx5e_cq *cq, int budget); /* RX */ INDIRECT_CALLABLE_DECLARE(bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c index 20994773056c..3c6c5a4692a3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c @@ -267,7 +267,7 @@ resync_post_get_progress_params(struct mlx5e_icosq *sq, goto err_out; } - pdev = mlx5_core_dma_dev(sq->channel->priv->mdev); + pdev = mlx5_core_dma_dev(sq->mdev); buf->dma_addr = dma_map_single(pdev, &buf->progress, PROGRESS_PARAMS_PADDED_SIZE, DMA_FROM_DEVICE); if (unlikely(dma_mapping_error(pdev, buf->dma_addr))) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 3aecdf099a2f..d517c385f9b5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -1500,6 +1500,7 @@ static int mlx5e_alloc_icosq(struct mlx5e_channel *c, int err; sq->channel = c; + sq->mdev = mdev; sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map; sq->reserved_room = param->stop_room; @@ -1898,11 +1899,9 @@ void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq) static void mlx5e_close_icosq(struct mlx5e_icosq *sq) { - struct mlx5e_channel *c = sq->channel; - if (sq->ktls_resync) mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync); - mlx5e_destroy_sq(c->mdev, sq->sqn); + mlx5e_destroy_sq(sq->mdev, sq->sqn); mlx5e_free_icosq_descs(sq); mlx5e_free_icosq(sq); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c index 8d9743a5e42c..addf8905fc35 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -993,7 +993,7 @@ static void mlx5e_handle_shampo_hd_umr(struct mlx5e_shampo_umr umr, shampo->ci = (shampo->ci + umr.len) & (shampo->hd_per_wq - 1); } -int mlx5e_poll_ico_cq(struct mlx5e_cq *cq) +int mlx5e_poll_ico_cq(struct mlx5e_cq *cq, int budget) { struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq); struct mlx5_cqe64 *cqe; @@ -1068,7 +1068,7 @@ int mlx5e_poll_ico_cq(struct mlx5e_cq *cq) wi->wqe_type); } } while (!last_wqe); - } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); + } while ((++i < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); sq->cc = sqcc; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c index a7d9b7cb4297..fd52311aada9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c @@ -178,8 +178,8 @@ int mlx5e_napi_poll(struct napi_struct *napi, int budget) busy |= work_done == budget; - mlx5e_poll_ico_cq(&c->icosq.cq); - if (mlx5e_poll_ico_cq(&c->async_icosq.cq)) + mlx5e_poll_ico_cq(&c->icosq.cq, MLX5E_TX_CQ_POLL_BUDGET); + if (mlx5e_poll_ico_cq(&c->async_icosq.cq, MLX5E_TX_CQ_POLL_BUDGET)) /* Don't clear the flag if nothing was polled to prevent * queueing more WQEs and overflowing the async ICOSQ. */