| Message ID | 20231129112155.9967-1-gakula@marvell.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [net-next] octeontx2-af: cn10k: Increase outstanding LMTST transactions | expand |
On Wed, Nov 29, 2023 at 04:51:55PM +0530, Geetha sowjanya wrote: > From: Pavan Nikhilesh <pbhagavatula@marvell.com> > > Currently the number of outstanding store transactions issued by AP as > a part of LMTST operation is set to 1 i.e default value. > This patch set to max supported value to increase the performance. > > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> > Signed-off-by: Geetha sowjanya <gakula@marvell.com> ... > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c > index 0e74c5a2231e..93fedabfe31e 100644 > --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c > +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c > @@ -559,3 +559,12 @@ void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw) > cfg |= BIT_ULL(1) | BIT_ULL(2); > rvu_write64(rvu, blkaddr, NIX_AF_CFG, cfg); > } > + > +void rvu_apr_block_cn10k_init(struct rvu *rvu) > +{ > + u64 reg; > + > + reg = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG); > + reg |= 0xFULL << 35; Hi Pavan and Geetha, I think it would be best to avoid the magic value 35 here. Best would probably be to use GENMASK_ULL and FIELD_PREP. Else defining something similar to APR_LMT_MAP_ENT_SCH_ENA_SHIFT. It might also be nice to avoid the magic value 0xFULL using a #define. > + rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CFG, reg); > +} > -- > 2.25.1 >
> -----Original Message----- > From: Simon Horman <horms@kernel.org> > Sent: Friday, December 1, 2023 5:05 PM > To: Geethasowjanya Akula <gakula@marvell.com> > Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org; kuba@kernel.org; > davem@davemloft.net; pabeni@redhat.com; edumazet@google.com; Sunil > Kovvuri Goutham <sgoutham@marvell.com>; Linu Cherian > <lcherian@marvell.com>; Jerin Jacob Kollanukkaran <jerinj@marvell.com>; > Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>; Subbaraya > Sundeep Bhatta <sbhatta@marvell.com>; Hariprasad Kelam > <hkelam@marvell.com> > Subject: [EXT] Re: [net-next PATCH] octeontx2-af: cn10k: Increase > outstanding LMTST transactions > > External Email > > ---------------------------------------------------------------------- > On Wed, Nov 29, 2023 at 04:51:55PM +0530, Geetha sowjanya wrote: > > From: Pavan Nikhilesh <pbhagavatula@marvell.com> > > > > Currently the number of outstanding store transactions issued by AP as > > a part of LMTST operation is set to 1 i.e default value. > > This patch set to max supported value to increase the performance. > > > > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> > > Signed-off-by: Geetha sowjanya <gakula@marvell.com> > > ... > > > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c > > b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c > > index 0e74c5a2231e..93fedabfe31e 100644 > > --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c > > +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c > > @@ -559,3 +559,12 @@ void rvu_nix_block_cn10k_init(struct rvu *rvu, > struct nix_hw *nix_hw) > > cfg |= BIT_ULL(1) | BIT_ULL(2); > > rvu_write64(rvu, blkaddr, NIX_AF_CFG, cfg); } > > + > > +void rvu_apr_block_cn10k_init(struct rvu *rvu) { > > + u64 reg; > > + > > + reg = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG); > > + reg |= 0xFULL << 35; > > Hi Pavan and Geetha, > > I think it would be best to avoid the magic value 35 here. > > Best would probably be to use GENMASK_ULL and FIELD_PREP. > Else defining something similar to APR_LMT_MAP_ENT_SCH_ENA_SHIFT. > > It might also be nice to avoid the magic value 0xFULL using a #define. Ack. Will submit next version. > > > + rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CFG, reg); } > > -- > > 2.25.1 > >
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c index 22c395c7d040..14bb91b98f97 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c @@ -935,6 +935,9 @@ static int rvu_setup_hw_resources(struct rvu *rvu) hw->total_vfs = (cfg >> 20) & 0xFFF; hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; + if (!is_rvu_otx2(rvu)) + rvu_apr_block_cn10k_init(rvu); + /* Init NPA LF's bitmap */ block = &hw->block[BLKADDR_NPA]; if (!block->implemented) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h index c4d999ef5ab4..6546cc489d7e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -940,6 +940,7 @@ void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw); /* CN10K RVU - LMT*/ void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); +void rvu_apr_block_cn10k_init(struct rvu *rvu); #ifdef CONFIG_DEBUG_FS void rvu_dbg_init(struct rvu *rvu); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c index 0e74c5a2231e..93fedabfe31e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c @@ -559,3 +559,12 @@ void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw) cfg |= BIT_ULL(1) | BIT_ULL(2); rvu_write64(rvu, blkaddr, NIX_AF_CFG, cfg); } + +void rvu_apr_block_cn10k_init(struct rvu *rvu) +{ + u64 reg; + + reg = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG); + reg |= 0xFULL << 35; + rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CFG, reg); +}