From patchwork Tue Dec 12 00:51:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Chan X-Patchwork-Id: 13488264 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="ZQN4RefR" Received: from mail-qt1-x829.google.com (mail-qt1-x829.google.com [IPv6:2607:f8b0:4864:20::829]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B56DC99 for ; Mon, 11 Dec 2023 16:51:57 -0800 (PST) Received: by mail-qt1-x829.google.com with SMTP id d75a77b69052e-425a3cdbda9so27442151cf.1 for ; Mon, 11 Dec 2023 16:51:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1702342317; x=1702947117; darn=vger.kernel.org; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:from:to:cc:subject:date:message-id:reply-to; bh=wNk0zqQYBMzO6jSvmAkJ8DG3IL4S0aPTPP4piHNAOYQ=; b=ZQN4RefRch3+ZpKp3ms0c3Pc7dJdGc0I/aBc1GlnTNxvXW6FoVI66gqDaRJi5aNsuA fv4Lsy7yBr7aKrT4PVx4w9KwTO0SjjEIlcE3qIIciiQaSqOwiAKbvK4l0FHU6lOw01lo pq8riYV9R/I6rZLGkUXGDL+qG0pfPTlqjl7Qw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702342317; x=1702947117; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=wNk0zqQYBMzO6jSvmAkJ8DG3IL4S0aPTPP4piHNAOYQ=; b=YYBkqW0l52XocP6lCp/buEWR+srV8cltStkRljUp5IsOIIdjEPwSx+XQ1lB/Zq1NSS exFInyjgwYKH8nj7bxTkfn/AhqC5WOxwRG5fHKBalI+cvoUFe+2uXepPT66RwKygvKFI rwMt+dKMK2AjHgQiH1DwiDOmLL7fxp1ouVFrfQAbBZZ/NJ1XiHujZviMAd9oLB6pXDc5 DF3o55gLrVcsLmME0b+AuYUNHhxeSxtf4qZ17anqMAgVLpQLOlVMvEV170ZD6lHO8nms 6t5HePxRyTJdVvlydrc2sGvQTj+oy3vRjFXHF76shMNjQ/mb/nfxvUMhhoKQKdaYyI7I nGhg== X-Gm-Message-State: AOJu0Yzzbi7vNq1EQn67rEcg2ypWRxHdYonoj6Im0dP5q8AEBK7SMPRe YJSKIbBYwDw+LLH0lyoFkQN0W3w8gGfKKqY7tp0= X-Google-Smtp-Source: AGHT+IHu5a4Z6KgbPBnUGX65KBfcvkWJBI568YEMSfZYFeTSHiRZDJ+CBIVGZ9a9cTi6FH3sYFD7Yw== X-Received: by 2002:a05:622a:244:b0:425:4042:f45f with SMTP id c4-20020a05622a024400b004254042f45fmr7402952qtx.67.1702342316783; Mon, 11 Dec 2023 16:51:56 -0800 (PST) Received: from lvnvda5233.lvn.broadcom.net ([192.19.161.250]) by smtp.gmail.com with ESMTPSA id r5-20020ac87945000000b00423ea1b31b3sm3619664qtt.66.2023.12.11.16.51.55 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Dec 2023 16:51:56 -0800 (PST) From: Michael Chan To: davem@davemloft.net Cc: netdev@vger.kernel.org, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, gospo@broadcom.com, Ajit Khaparde Subject: [PATCH net-next 09/13] bnxt_en: Configure UDP tunnel TPA Date: Mon, 11 Dec 2023 16:51:18 -0800 Message-Id: <20231212005122.2401-10-michael.chan@broadcom.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20231212005122.2401-1-michael.chan@broadcom.com> References: <20231212005122.2401-1-michael.chan@broadcom.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org On the new P7 chips, TPA for tunnel packets can be independently enabled for each VNIC. The default TPA configuration should not include UDP tunnels because the UDP ports for these tunnels are not known yet. The chip should not aggregate these UDP tunneled packets using default UDP ports until the ports are known. Add a new function bnxt_hwrm_vnic_update_tunl_tpa() to enable VXLAN and Geneve TPA if the corresponding UDP ports are known. Reviewed-by: Ajit Khaparde Signed-off-by: Michael Chan --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 33 +++++++++++++++++++++++ drivers/net/ethernet/broadcom/bnxt/bnxt.h | 1 + 2 files changed, 34 insertions(+) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index b9eb3e0c5995..3594290e187a 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -5150,6 +5150,8 @@ int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) return hwrm_req_send(bp, req); } +static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa); + static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) { struct hwrm_tunnel_dst_port_free_input *req; @@ -5192,6 +5194,8 @@ static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) if (rc) netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", rc); + if (bp->flags & BNXT_FLAG_TPA) + bnxt_set_tpa(bp, true); return rc; } @@ -5235,6 +5239,8 @@ static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, default: break; } + if (bp->flags & BNXT_FLAG_TPA) + bnxt_set_tpa(bp, true); err_out: hwrm_req_drop(bp, req); @@ -5427,6 +5433,30 @@ static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) return rc; } +#define BNXT_DFLT_TUNL_TPA_BMAP \ + (VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE | \ + VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV4 | \ + VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV6) + +static void bnxt_hwrm_vnic_update_tunl_tpa(struct bnxt *bp, + struct hwrm_vnic_tpa_cfg_input *req) +{ + u32 tunl_tpa_bmap = BNXT_DFLT_TUNL_TPA_BMAP; + + if (!(bp->fw_cap & BNXT_FW_CAP_VNIC_TUNNEL_TPA)) + return; + + if (bp->vxlan_port) + tunl_tpa_bmap |= VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN; + if (bp->vxlan_gpe_port) + tunl_tpa_bmap |= VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_GPE; + if (bp->nge_port) + tunl_tpa_bmap |= VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GENEVE; + + req->enables |= cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_TNL_TPA_EN); + req->tnl_tpa_en_bitmap = cpu_to_le32(tunl_tpa_bmap); +} + static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) { struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; @@ -5483,6 +5513,7 @@ static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) req->max_aggs = cpu_to_le16(max_aggs); req->min_agg_len = cpu_to_le32(512); + bnxt_hwrm_vnic_update_tunl_tpa(bp, req); } req->vnic_id = cpu_to_le16(vnic->fw_vnic_id); @@ -5977,6 +6008,8 @@ static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) else bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P7; } + if (flags & VNIC_QCAPS_RESP_FLAGS_HW_TUNNEL_TPA_CAP) + bp->fw_cap |= BNXT_FW_CAP_VNIC_TUNNEL_TPA; } hwrm_req_drop(bp, req); return rc; diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.h b/drivers/net/ethernet/broadcom/bnxt/bnxt.h index 609f4073f5ff..15d33f4a61c2 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.h +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.h @@ -2240,6 +2240,7 @@ struct bnxt { #define BNXT_FW_CAP_DFLT_VLAN_TPID_PCP BIT_ULL(34) #define BNXT_FW_CAP_PRE_RESV_VNICS BIT_ULL(35) #define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(36) + #define BNXT_FW_CAP_VNIC_TUNNEL_TPA BIT_ULL(37) u32 fw_dbg_cap;