From patchwork Tue Dec 12 00:51:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Chan X-Patchwork-Id: 13488260 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="fdnASrfP" Received: from mail-qt1-x829.google.com (mail-qt1-x829.google.com [IPv6:2607:f8b0:4864:20::829]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B38AF99 for ; Mon, 11 Dec 2023 16:51:51 -0800 (PST) Received: by mail-qt1-x829.google.com with SMTP id d75a77b69052e-4259cd18f85so29506651cf.3 for ; Mon, 11 Dec 2023 16:51:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1702342311; x=1702947111; darn=vger.kernel.org; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:from:to:cc:subject:date:message-id:reply-to; bh=0GRg3tTFnd1ThzcDN5BotumcET1n98r4nqdLd+1/9JM=; b=fdnASrfPK/x21RTyibo363r5cUc9OIVrkF4OJHKNhMF+JPhbL0K0VxXxgmabPsH46c bAOuYVCY7Emvfq+xJSrFI7QgT9xleooXq7CHNH0bGab1le890vj+ex4rDJeUgN/jN1Kw nFlxpytRXKH4fXRRFjsRXk16IMlH2GNd81G0U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702342311; x=1702947111; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=0GRg3tTFnd1ThzcDN5BotumcET1n98r4nqdLd+1/9JM=; b=dxWdhper1SEvmvKavDAz53haVn9CBIgisH79sD8y/QtLZIQIBqP2gJVzMJ5VrRifGy Djtmr4LIBLU8Hv+v29nk0cuIGd81zPeIxF2KvMxVzEMG1M2kc5Tq0rfMRKdolVaalXwI 3eIWfA7gq+houys4EumDJJQ9SgHRudKIV5egMXcg/MENyx2I/V+bX3BWUecAxVlHTEp6 Hek8sdBmuYzDb74Q/RurJvyfa9fCf3V0qALN3tM9+RloH/GfYJ9bqz5N20y9kecUKo+c QbCanAZeILXeJYRiy2VY89AZ8Tn35QuViYQ81dTfI7FXboqyRcWdcEwzAFpS1TMec49O OusA== X-Gm-Message-State: AOJu0YzWIa7V19LDgA0KxQu8orsm5gKjpm9yiNFByGBr5p5oDzrf/oHp HNbMH1jSJacw8CE48fDn2SZm5g== X-Google-Smtp-Source: AGHT+IE5KkuGXZbRzG2M6AVpsZWUMHWXImPYSUcpzCiBDezEOyYf2r9UxlK7Wuw+dqjq0CnBkLHwpw== X-Received: by 2002:ac8:7d52:0:b0:425:4043:7650 with SMTP id h18-20020ac87d52000000b0042540437650mr8206344qtb.120.1702342310721; Mon, 11 Dec 2023 16:51:50 -0800 (PST) Received: from lvnvda5233.lvn.broadcom.net ([192.19.161.250]) by smtp.gmail.com with ESMTPSA id r5-20020ac87945000000b00423ea1b31b3sm3619664qtt.66.2023.12.11.16.51.49 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Dec 2023 16:51:50 -0800 (PST) From: Michael Chan To: davem@davemloft.net Cc: netdev@vger.kernel.org, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, gospo@broadcom.com Subject: [PATCH net-next 05/13] bnxt_en: Support TX coalesced completion on 5760X chips Date: Mon, 11 Dec 2023 16:51:14 -0800 Message-Id: <20231212005122.2401-6-michael.chan@broadcom.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20231212005122.2401-1-michael.chan@broadcom.com> References: <20231212005122.2401-1-michael.chan@broadcom.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org TX coalesced completions are supported on newer chips to provide one TX completion record for multiple TX packets up to the sq_cons_idx in the completion record. This method saves PCIe bandwidth by reducing the number of TX completions. Only very minor changes are now required to support this mode with the new framework that handles TX completions based on the consumer indices. Signed-off-by: Michael Chan --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 13 +++++++++++-- drivers/net/ethernet/broadcom/bnxt/bnxt.h | 1 + 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index cc6cab340423..72e2bd4611de 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -2785,14 +2785,18 @@ static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, */ dma_rmb(); cmp_type = TX_CMP_TYPE(txcmp); - if (cmp_type == CMP_TYPE_TX_L2_CMP) { + if (cmp_type == CMP_TYPE_TX_L2_CMP || + cmp_type == CMP_TYPE_TX_L2_COAL_CMP) { u32 opaque = txcmp->tx_cmp_opaque; struct bnxt_tx_ring_info *txr; u16 tx_freed; txr = bnapi->tx_ring[TX_OPAQUE_RING(opaque)]; event |= BNXT_TX_CMP_EVENT; - txr->tx_hw_cons = TX_OPAQUE_PROD(bp, opaque); + if (cmp_type == CMP_TYPE_TX_L2_COAL_CMP) + txr->tx_hw_cons = TX_CMP_SQ_CONS_IDX(txcmp); + else + txr->tx_hw_cons = TX_OPAQUE_PROD(bp, opaque); tx_freed = (txr->tx_hw_cons - txr->tx_cons) & bp->tx_ring_mask; /* return full budget so NAPI will complete. */ @@ -6068,6 +6072,9 @@ static int hwrm_ring_alloc_send_msg(struct bnxt *bp, req->length = cpu_to_le32(bp->tx_ring_mask + 1); req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); req->queue_id = cpu_to_le16(ring->queue_id); + if (bp->flags & BNXT_FLAG_TX_COAL_CMPL) + req->cmpl_coal_cnt = + RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64; break; } case HWRM_RING_ALLOC_RX: @@ -8279,6 +8286,8 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) bp->fw_cap |= BNXT_FW_CAP_LIVEPATCH; if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED) bp->fw_cap |= BNXT_FW_CAP_BACKING_STORE_V2; + if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP) + bp->flags |= BNXT_FLAG_TX_COAL_CMPL; flags_ext2 = le32_to_cpu(resp->flags_ext2); if (flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.h b/drivers/net/ethernet/broadcom/bnxt/bnxt.h index afa784305fea..67915ab13f50 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.h +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.h @@ -2047,6 +2047,7 @@ struct bnxt { #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000 #define BNXT_FLAG_DIM 0x2000000 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000 + #define BNXT_FLAG_TX_COAL_CMPL 0x8000000 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \