From patchwork Wed Jan 3 14:28:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Romain Gantois X-Patchwork-Id: 13510124 X-Patchwork-Delegate: kuba@kernel.org Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3ABD41A71F; Wed, 3 Jan 2024 14:28:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="NLIgcVMN" Received: by mail.gandi.net (Postfix) with ESMTPSA id 043CD6000D; Wed, 3 Jan 2024 14:28:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1704292109; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hmed1jEpoZI+pixYHArlZGQKHPpdNarPzqdiGktR7JI=; b=NLIgcVMNlWi0/VrDdnLc+QqsaPfWKXhZvk1NqViiDyZoMs1+PEZ28REKDlv2RaCmv99Ia7 O3cKXIDjObnrrQ3k0kn9fwsvvKqeQYbdKq+GSSSPXeT6XihHjUEddonlcvdgea4nUuiYj3 FfWkiCOgoXFtcJjzjK2S9E9j3GmrLOlKufDkFOhe7QRchKn+MgCN8eO0Z8lB6sJEzSZtQ3 h4YuROcxNvOczQb+kJni36zKsewpgKSiObzwFvhwbiPjq3rGXm0z+aQI92ISmJuj5KketI D1tZS5HrIcfnYpp1E8jLoIKm6Ii3WoXpr7EpCo0gY1IqmDHEW5buHcXJxCOeYQ== From: Romain Gantois To: Alexandre Torgue , Jose Abreu , Russell King , Andrew Lunn , Jakub Kicinski , Heiner Kallweit Cc: Romain Gantois , "David S. Miller" , Eric Dumazet , Paolo Abeni , Maxime Coquelin , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Marek Vasut , Clark Wang , Miquel Raynal , Sylvain Girard , Pascal EBERHARD , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH net 5/5] net: pcs: rzn1-miic: Init RX clock early if MAC requires it Date: Wed, 3 Jan 2024 15:28:25 +0100 Message-ID: <20240103142827.168321-6-romain.gantois@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103142827.168321-1-romain.gantois@bootlin.com> References: <20240103142827.168321-1-romain.gantois@bootlin.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: romain.gantois@bootlin.com X-Patchwork-Delegate: kuba@kernel.org The GMAC1 controller in the RZN1 IP requires the RX MII clock signal to be started before it initializes its own hardware, thus before it calls phylink_start. Check the rxc_always_on pcs flag and enable the clock signal during the link validation phase. Reported-by: Clément Léger Link: https://lore.kernel.org/linux-arm-kernel/20230116103926.276869-4-clement.leger@bootlin.com/ Signed-off-by: Romain Gantois --- drivers/net/pcs/pcs-rzn1-miic.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c index 97139c07130f..bf796491b826 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -271,12 +271,20 @@ static void miic_link_up(struct phylink_pcs *pcs, unsigned int mode, static int miic_validate(struct phylink_pcs *pcs, unsigned long *supported, const struct phylink_link_state *state) { - if (phy_interface_mode_is_rgmii(state->interface) || - state->interface == PHY_INTERFACE_MODE_RMII || - state->interface == PHY_INTERFACE_MODE_MII) - return 1; + int ret = 1; - return -EINVAL; + if (!phy_interface_mode_is_rgmii(state->interface) && + state->interface != PHY_INTERFACE_MODE_RMII && + state->interface != PHY_INTERFACE_MODE_MII) + return -EINVAL; + + if (pcs->rxc_always_on) { + ret = miic_config(pcs, 0, state->interface, NULL, false); + if (ret) + pr_err("Error: Failed to init RX clock in RZN1 MIIC PCS!"); + } + + return ret; } static const struct phylink_pcs_ops miic_phylink_ops = {