diff mbox series

[4/6] arm64: dts: qcom: ipq9574: Add MDIO device tree

Message ID 20240110112059.2498-5-quic_luoj@quicinc.com (mailing list archive)
State Not Applicable
Headers show
Series Add PPE device tree node for Qualcomm IPQ SoC | expand

Checks

Context Check Description
netdev/tree_selection success Not a local patch

Commit Message

Luo Jie Jan. 10, 2024, 11:20 a.m. UTC 
Add MDIO device tree of ipq9574.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 28 +++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 5fa241e27c8b..cf21ce9bf756 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -316,6 +316,22 @@  uart2_pins: uart2-state {
 				drive-strength = <8>;
 				bias-disable;
 			};
+
+			mdio_pins: mdio-state {
+				mux_0 {
+					pins = "gpio38";
+					function = "mdc";
+					drive-strength = <8>;
+					bias-disable;
+				};
+
+				mux_1 {
+					pins = "gpio39";
+					function = "mdio";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+			};
 		};
 
 		gcc: clock-controller@1800000 {
@@ -1503,6 +1519,18 @@  group0 {
 				};
 			};
 		};
+
+		mdio: mdio@90000 {
+			compatible = "qcom,ipq4019-mdio";
+			reg = <0x90000 0x64>;
+			pinctrl-0 = <&mdio_pins>;
+			pinctrl-names = "default";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&gcc GCC_MDIO_AHB_CLK>;
+			clock-names = "gcc_mdio_ahb_clk";
+			status = "disabled";
+		};
 	};
 
 	thermal-zones {