| Message ID | 20240110112059.2498-6-quic_luoj@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | Add PPE device tree node for Qualcomm IPQ SoC | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Not a local patch |
On 10/01/2024 12:20, Luo Jie wrote: > From: Lei Wei <quic_leiwei@quicinc.com> > > RDP441 board has onboard QCA8386 switch and 10G SFP port. > > Signed-off-by: Lei Wei <quic_leiwei@quicinc.com> > Signed-off-by: Luo Jie <quic_luoj@quicinc.com> > --- > arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 51 +++++++++++++++++++++ > 1 file changed, 51 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts > index 846413817e9a..d51968e9d601 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts > +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts > @@ -12,6 +12,15 @@ > / { > model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; > compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; > + > + soc@0 { Nope, DTS does not define soc nodes. > + sfp1: sfp-1 { Why is this soc? Where is the MMIO address? > + compatible = "sff,sfp"; > + i2c-bus = <&blsp1_i2c1>; > + los-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; > + tx-disable-gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>; > + }; > + }; > }; > > &blsp1_i2c1 { > @@ -63,3 +72,45 @@ data-pins { > }; > }; > }; > + > +&qcom_ppe { > + qcom,port_phyinfo { Eh... We talk now about basics: please don't post downstream code, but first clean it up from all the junk. All the basic issues which you have in downstream and which we do not accept upstream. I do not believe that this code passed internal review. NAK. Best regards, Krzysztof
On 1/10/2024 7:57 PM, Krzysztof Kozlowski wrote: > On 10/01/2024 12:20, Luo Jie wrote: >> From: Lei Wei <quic_leiwei@quicinc.com> >> >> RDP441 board has onboard QCA8386 switch and 10G SFP port. >> >> Signed-off-by: Lei Wei <quic_leiwei@quicinc.com> >> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 51 +++++++++++++++++++++ >> 1 file changed, 51 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts >> index 846413817e9a..d51968e9d601 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts >> +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts >> @@ -12,6 +12,15 @@ >> / { >> model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; >> compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; >> + >> + soc@0 { > > Nope, DTS does not define soc nodes. > OK, I will remove the soc node in the DTS file. SFP node should not be inside the soc node. >> + sfp1: sfp-1 { > > Why is this soc? Where is the MMIO address? Sure, SoC node should not be required. I will remove the soc node. > >> + compatible = "sff,sfp"; >> + i2c-bus = <&blsp1_i2c1>; >> + los-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; >> + tx-disable-gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>; >> + }; >> + }; >> }; >> >> &blsp1_i2c1 { >> @@ -63,3 +72,45 @@ data-pins { >> }; >> }; >> }; >> + >> +&qcom_ppe { >> + qcom,port_phyinfo { > > Eh... We talk now about basics: please don't post downstream code, but > first clean it up from all the junk. All the basic issues which you have > in downstream and which we do not accept upstream. > > I do not believe that this code passed internal review. > > NAK. Sure, got it. I will follow the upstream principles to use generic node name. > > Best regards, > Krzysztof >
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 846413817e9a..d51968e9d601 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -12,6 +12,15 @@ / { model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; + + soc@0 { + sfp1: sfp-1 { + compatible = "sff,sfp"; + i2c-bus = <&blsp1_i2c1>; + los-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>; + }; + }; }; &blsp1_i2c1 { @@ -63,3 +72,45 @@ data-pins { }; }; }; + +&qcom_ppe { + qcom,port_phyinfo { + ppe_port0: port@0 { + port_id = <1>; + phy-mode = "2500base-x"; + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + ppe_port1: port@1 { + port_id = <2>; + phy-mode = "10gbase-r"; + sfp = <&sfp1>; + managed = "in-band-status"; + }; + }; +}; + +&mdio { + status = "okay"; + reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>; + + phy0: ethernet-phy@0 { + reg = <1>; + }; + + phy1: ethernet-phy@1 { + reg = <2>; + }; + + phy2: ethernet-phy@2 { + reg = <3>; + }; + + phy3: ethernet-phy@3 { + reg = <4>; + }; +};