From patchwork Thu Feb 8 05:51:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= X-Patchwork-Id: 13549328 X-Patchwork-Delegate: kuba@kernel.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B77567C58; Thu, 8 Feb 2024 05:51:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707371493; cv=none; b=nZQOOjEuYfhBi2TFhlQVbV8LeKonVoXTQtuG7a1Cy7MfawCriqmp0rklmxT3eeRsy/O5S9X8goeLCOiSW/kRnReZRATXelP5QJovK5cTiXdjlVMf6H8mGK+DikcAGMBv1JcrpjhbLKtDvoFboyHy3CVAEmP+VfeLGdhWo56xyfM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707371493; c=relaxed/simple; bh=wUpyw43HcHACBQ/8AUAV0rAR4ahB+zKQE8l7LVuV9Hs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=R5iFPvF205TJ8P6SwCLWwDgr3yX74QlrV3FPRn5yiDM5UALFN2nV+CpmreWy3moapLnZPlD1POhy6Rih/4PUtqiZgwpF7w6BSfawI0ZZStLxVSGzU5ZlrNRc8ClZlPel10teAtjcU8GdxBC8aDFwlw3368IegvvnRcha5jiLcfQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cBHOSC7y; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cBHOSC7y" Received: by smtp.kernel.org (Postfix) with ESMTPS id 39B60C433A6; Thu, 8 Feb 2024 05:51:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1707371493; bh=wUpyw43HcHACBQ/8AUAV0rAR4ahB+zKQE8l7LVuV9Hs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=cBHOSC7yaVTnS02Cyl5GFht/49PLZEWbToeZA1f3LgwWor/PoTHEWZpefJoUgPiSk OoVYW4ReJNmizZN4RebdXp2JRM48fdCnknKIGcyTQ2be0b9MdT1Y0u+AZ+dHi6bFKl 4jrTVL4gvxm0gsS8iEUYdhNAtZmeAKBGVJC+oBz/sXwK7j9eH9u4v2aLuXvECNcK36 j+8suBpSxPlC7mXSqT82PVkvb4xjxvTkcAxYBVB5Yyz0U+VRlOwj7cTofPbysKVf7w 8i4mN4/0/LVJ0od3RcxD7odaz6SmVU0IvVAmy1COIRIBQEy4UajiGHtIEMsADsyA+i vjIf7GYUx/xvQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24E64C4829F; Thu, 8 Feb 2024 05:51:33 +0000 (UTC) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= via B4 Relay Date: Thu, 08 Feb 2024 08:51:31 +0300 Subject: [PATCH netnext 3/8] net: dsa: mt7530: do not use SW_PHY_RST to reset MT7531 switch Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240208-for-netnext-mt7530-improvements-3-v1-3-d7c1cfd502ca@arinc9.com> References: <20240208-for-netnext-mt7530-improvements-3-v1-0-d7c1cfd502ca@arinc9.com> In-Reply-To: <20240208-for-netnext-mt7530-improvements-3-v1-0-d7c1cfd502ca@arinc9.com> To: Daniel Golle , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: mithat.guner@xeront.com, erkin.bozoglu@xeront.com, Bartel Eerdekens , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707371489; l=1298; i=arinc.unal@arinc9.com; s=arinc9-patatt; h=from:subject:message-id; bh=ecurYkRWOTqqGU2AKHni4Fzup3XR61+gzZ3STlqM5Z4=; b=b9VDNMoY49Q3hQXGaelaQQGU9njla99nADPmBBsMFgG6+sLkgV6dTFLgcxR3xwicbe8v5YjB/ QUbfKb63s/bAWQS4VVEgivcMh5LXkwLvTS/ghzQdKgOVOMBAzfkIBiJ X-Developer-Key: i=arinc.unal@arinc9.com; a=ed25519; pk=VmvgMWwm73yVIrlyJYvGtnXkQJy9CvbaeEqPQO9Z4kA= X-Endpoint-Received: by B4 Relay for arinc.unal@arinc9.com/arinc9-patatt with auth_id=115 X-Original-From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= Reply-To: X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL According to the document MT7531 Reference Manual for Development Board v1.0, the SW_PHY_RST bit on the SYS_CTRL register doesn't exist for MT7531. This is likely why forcing link down on all ports is necessary for MT7531. Therefore, do not set SW_PHY_RST on mt7531_setup(). Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 5cfd303b773f..296711fd5c43 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2451,14 +2451,12 @@ mt7531_setup(struct dsa_switch *ds) val = mt7530_read(priv, MT7531_TOP_SIG_SR); priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); - /* all MACs must be forced link-down before sw reset */ + /* Force link down on all ports before internal reset */ for (i = 0; i < MT7530_NUM_PORTS; i++) mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); /* Reset the switch through internal reset */ - mt7530_write(priv, MT7530_SYS_CTRL, - SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | - SYS_CTRL_REG_RST); + mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); if (!priv->p5_sgmii) { mt7531_pll_setup(priv);