| Message ID | 20240216-net-v1-4-e0ad972cda99@outlook.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: hisi-femac: add support for Hi3798MV200, remove unmaintained compatibles | expand |
> + clocks: > + minItems: 3 > + maxItems: 3 > + > + clock-names: > + items: > + - const: mac > + - const: macif > + - const: phy The C code has: +enum clk_type { + CLK_MAC, + CLK_BUS, + CLK_PHY, + CLK_NUM, +}; Could you explain BUS vs macif? Also, what exactly is the PHY clock? Andrew
On 2/16/2024 8:06 AM, Andrew Lunn wrote: >> + clocks: >> + minItems: 3 >> + maxItems: 3 >> + >> + clock-names: >> + items: >> + - const: mac >> + - const: macif >> + - const: phy > The C code has: > > +enum clk_type { > + CLK_MAC, > + CLK_BUS, > + CLK_PHY, > + CLK_NUM, > +}; > > Could you explain BUS vs macif? To be honest, I don't know. "macif" is used by hisi-gmac driver, but in the TRM it's called "bus". So I guess it's just an alias? As you mentioned, I'll stick to macif everywhere, to keep sync with hisi-gmac driver. > > Also, what exactly is the PHY clock? As the name suggests, it's not part of the mac controller actually, rather it's the clock of the internal PHY. The SoC (or the PHY/MAC, I don't know exactly which) is quirky that it is mandatory to disable PHY CLK before MAC reset or else the PHY won't work(see hisi_femac_phy_reset()). I can't find a better solution. Letting the ethernet controller manage all clocks and resets seems the easiest way to handle this quirk. > > Andrew
On Fri, 16 Feb 2024 07:48:56 +0800, Yang Xiwen wrote: > This binding gets rewritten. Compared to previous txt based binding doc, > the following changes are made: > > - No "hisi-femac-v1/2" binding anymore > - Remove unused Hi3516 SoC, add Hi3798MV200 > - add MDIO subnode > - add phy clock and reset > > Signed-off-by: Yang Xiwen <forbidden405@outlook.com> > --- > .../devicetree/bindings/net/hisilicon-femac.yaml | 125 +++++++++++++++++++++ > 1 file changed, 125 insertions(+) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/net/hisilicon-femac.example.dtb: /example-0/ethernet@9c30000/mdio@1100: failed to match any schema with compatible: ['hisilicon,hisi-femac-mdio'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240216-net-v1-4-e0ad972cda99@outlook.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On 2/16/2024 10:09 AM, Rob Herring wrote: > On Fri, 16 Feb 2024 07:48:56 +0800, Yang Xiwen wrote: >> This binding gets rewritten. Compared to previous txt based binding doc, >> the following changes are made: >> >> - No "hisi-femac-v1/2" binding anymore >> - Remove unused Hi3516 SoC, add Hi3798MV200 >> - add MDIO subnode >> - add phy clock and reset >> >> Signed-off-by: Yang Xiwen <forbidden405@outlook.com> >> --- >> .../devicetree/bindings/net/hisilicon-femac.yaml | 125 +++++++++++++++++++++ >> 1 file changed, 125 insertions(+) >> > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Documentation/devicetree/bindings/net/hisilicon-femac.example.dtb: /example-0/ethernet@9c30000/mdio@1100: failed to match any schema with compatible: ['hisilicon,hisi-femac-mdio'] it's fine. This compatible is documented in a plain text file `./hisi-femac-mdio.txt`. > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240216-net-v1-4-e0ad972cda99@outlook.com > > The base for the series is generally the latest rc1. A different dependency > should be noted in *this* patch. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit after running the above command yourself. Note > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > your schema. However, it must be unset to test all examples with your schema. >
On 16/02/2024 07:30, Yang Xiwen wrote: > On 2/16/2024 10:09 AM, Rob Herring wrote: >> On Fri, 16 Feb 2024 07:48:56 +0800, Yang Xiwen wrote: >>> This binding gets rewritten. Compared to previous txt based binding doc, >>> the following changes are made: >>> >>> - No "hisi-femac-v1/2" binding anymore >>> - Remove unused Hi3516 SoC, add Hi3798MV200 >>> - add MDIO subnode >>> - add phy clock and reset >>> >>> Signed-off-by: Yang Xiwen <forbidden405@outlook.com> >>> --- >>> .../devicetree/bindings/net/hisilicon-femac.yaml | 125 +++++++++++++++++++++ >>> 1 file changed, 125 insertions(+) >>> >> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' >> on your patch (DT_CHECKER_FLAGS is new in v5.13): >> >> yamllint warnings/errors: >> >> dtschema/dtc warnings/errors: >> Documentation/devicetree/bindings/net/hisilicon-femac.example.dtb: /example-0/ethernet@9c30000/mdio@1100: failed to match any schema with compatible: ['hisilicon,hisi-femac-mdio'] > it's fine. This compatible is documented in a plain text file > `./hisi-femac-mdio.txt`. No, it is not fine. This must be fixed. Best regards, Krzysztof
On 16/02/2024 00:48, Yang Xiwen via B4 Relay wrote: > From: Yang Xiwen <forbidden405@outlook.com> > > This binding gets rewritten. Compared to previous txt based binding doc, > the following changes are made: > > - No "hisi-femac-v1/2" binding anymore > - Remove unused Hi3516 SoC, add Hi3798MV200 > - add MDIO subnode > - add phy clock and reset I don't understand why conversion you make in two commits. Please perform proper conversion and then propose changes to the binding. > > Signed-off-by: Yang Xiwen <forbidden405@outlook.com> > --- > .../devicetree/bindings/net/hisilicon-femac.yaml | 125 +++++++++++++++++++++ > 1 file changed, 125 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/hisilicon-femac.yaml b/Documentation/devicetree/bindings/net/hisilicon-femac.yaml > new file mode 100644 > index 000000000000..008127e148aa > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/hisilicon-femac.yaml Use compatible as filename. > @@ -0,0 +1,125 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/hisilicon-femac.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Hisilicon Fast Ethernet MAC controller > + > +maintainers: > + - Yang Xiwen <forbidden405@foxmail.com> > + > +allOf: > + - $ref: ethernet-controller.yaml > + > +properties: > + compatible: > + enum: > + - hisilicon,hi3798mv200-femac > + > + reg: > + minItems: 2 > + maxItems: 2 > + description: | > + The first region is the MAC core register base and size. > + The second region is the global MAC control register. Just items: - description: instead of all this. > + > + ranges: > + maxItems: 1 > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + minItems: 3 Drop > + maxItems: 3 > + > + clock-names: > + items: > + - const: mac > + - const: macif > + - const: phy > + > + resets: > + minItems: 2 Drop > + maxItems: 2 > + > + reset-names: > + items: > + - const: mac > + - const: phy > + > + hisilicon,phy-reset-delays-us: > + minItems: 3 > + maxItems: 3 > + description: | > + The 1st cell is reset pre-delay in micro seconds. > + The 2nd cell is reset pulse in micro seconds. > + The 3rd cell is reset post-delay in micro seconds. items: - description: Anyway, isn't this property of the phy? > + > +patternProperties: > + '^mdio@[0-9a-f]+$': > + type: object > + description: See ./hisi-femac-mdio.txt No, please first convert other file and then reference it here. > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - resets > + - reset-names > + - phy-connection-type > + - phy-handle > + - hisilicon,phy-reset-delays-us > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/histb-clock.h> > + > + #ifndef HISTB_ETH0_PHY_CLK > + #define HISTB_ETH0_PHY_CLK 0 > + #endif Drop these defines. > + femac: ethernet@9c30000 { Drop label. > + compatible = "hisilicon,hi3798mv200-femac"; > + reg = <0x9c30000 0x1000>, <0x9c31300 0x200>; > + ranges = <0x0 0x9c30000 0x10000>; > + #address-cells = <1>; > + #size-cells = <1>; > + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&crg HISTB_ETH0_MAC_CLK>, > + <&crg HISTB_ETH0_MACIF_CLK>, > + <&crg HISTB_ETH0_PHY_CLK>; > + clock-names = "mac", "macif", "phy"; > + resets = <&crg 0xd0 3>, <&crg 0x388 4>; > + reset-names = "mac", "phy"; > + phy-handle = <&fephy>; > + phy-connection-type = "mii"; > + // To be filled by bootloader > + mac-address = [00 00 00 00 00 00]; > + hisilicon,phy-reset-delays-us = <10000 10000 500000>; > + status = "okay"; Drop > + > + mdio: mdio@1100 { Drop label > + compatible = "hisilicon,hisi-femac-mdio"; > + reg = <0x1100 0x20>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "okay"; Drop > + > + fephy: ethernet-phy@1 { Drop label > + reg = <1>; > + #phy-cells = <0>; > + }; > + }; > + }; > Best regards, Krzysztof
On 2/16/2024 3:24 PM, Krzysztof Kozlowski wrote: > On 16/02/2024 00:48, Yang Xiwen via B4 Relay wrote: >> From: Yang Xiwen <forbidden405@outlook.com> >> >> This binding gets rewritten. Compared to previous txt based binding doc, >> the following changes are made: >> >> - No "hisi-femac-v1/2" binding anymore >> - Remove unused Hi3516 SoC, add Hi3798MV200 >> - add MDIO subnode >> - add phy clock and reset > I don't understand why conversion you make in two commits. Please > perform proper conversion and then propose changes to the binding. > >> Signed-off-by: Yang Xiwen <forbidden405@outlook.com> >> --- >> .../devicetree/bindings/net/hisilicon-femac.yaml | 125 +++++++++++++++++++++ >> 1 file changed, 125 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/net/hisilicon-femac.yaml b/Documentation/devicetree/bindings/net/hisilicon-femac.yaml >> new file mode 100644 >> index 000000000000..008127e148aa >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/net/hisilicon-femac.yaml > Use compatible as filename. > >> @@ -0,0 +1,125 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/net/hisilicon-femac.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Hisilicon Fast Ethernet MAC controller >> + >> +maintainers: >> + - Yang Xiwen <forbidden405@foxmail.com> >> + >> +allOf: >> + - $ref: ethernet-controller.yaml >> + >> +properties: >> + compatible: >> + enum: >> + - hisilicon,hi3798mv200-femac >> + >> + reg: >> + minItems: 2 >> + maxItems: 2 >> + description: | >> + The first region is the MAC core register base and size. >> + The second region is the global MAC control register. > Just items: - description: instead of all this. > >> + >> + ranges: >> + maxItems: 1 >> + >> + '#address-cells': >> + const: 1 >> + >> + '#size-cells': >> + const: 1 >> + >> + interrupts: >> + maxItems: 1 >> + >> + clocks: >> + minItems: 3 > Drop > >> + maxItems: 3 >> + >> + clock-names: >> + items: >> + - const: mac >> + - const: macif >> + - const: phy >> + >> + resets: >> + minItems: 2 > Drop > >> + maxItems: 2 >> + >> + reset-names: >> + items: >> + - const: mac >> + - const: phy >> + >> + hisilicon,phy-reset-delays-us: >> + minItems: 3 >> + maxItems: 3 >> + description: | >> + The 1st cell is reset pre-delay in micro seconds. >> + The 2nd cell is reset pulse in micro seconds. >> + The 3rd cell is reset post-delay in micro seconds. > items: > - description: > > Anyway, isn't this property of the phy? It ought to be. But it seems a bit hard to implement it like this. > > >> + >> +patternProperties: >> + '^mdio@[0-9a-f]+$': >> + type: object >> + description: See ./hisi-femac-mdio.txt > No, please first convert other file and then reference it here. > >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - clocks >> + - clock-names >> + - resets >> + - reset-names >> + - phy-connection-type >> + - phy-handle >> + - hisilicon,phy-reset-delays-us >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + #include <dt-bindings/clock/histb-clock.h> >> + >> + #ifndef HISTB_ETH0_PHY_CLK >> + #define HISTB_ETH0_PHY_CLK 0 >> + #endif > Drop these defines. It is depending on a local patch which update include/dt-bindings/clock/histb-clock.h. But currently i'm not going to sent it since i'm still tweaking clock drivers frequently. Removing these defines now would probably leads to a compile error. Or I can just change them to some magic numbers. > >> + femac: ethernet@9c30000 { > Drop label. > >> + compatible = "hisilicon,hi3798mv200-femac"; >> + reg = <0x9c30000 0x1000>, <0x9c31300 0x200>; >> + ranges = <0x0 0x9c30000 0x10000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&crg HISTB_ETH0_MAC_CLK>, >> + <&crg HISTB_ETH0_MACIF_CLK>, >> + <&crg HISTB_ETH0_PHY_CLK>; >> + clock-names = "mac", "macif", "phy"; >> + resets = <&crg 0xd0 3>, <&crg 0x388 4>; >> + reset-names = "mac", "phy"; >> + phy-handle = <&fephy>; >> + phy-connection-type = "mii"; >> + // To be filled by bootloader >> + mac-address = [00 00 00 00 00 00]; >> + hisilicon,phy-reset-delays-us = <10000 10000 500000>; >> + status = "okay"; > Drop > >> + >> + mdio: mdio@1100 { > Drop label > >> + compatible = "hisilicon,hisi-femac-mdio"; >> + reg = <0x1100 0x20>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "okay"; > Drop > >> + >> + fephy: ethernet-phy@1 { > Drop label > > >> + reg = <1>; >> + #phy-cells = <0>; >> + }; >> + }; >> + }; >> > Best regards, > Krzysztof >
On 16/02/2024 10:36, Yang Xiwen wrote: >> >>> + maxItems: 2 >>> + >>> + reset-names: >>> + items: >>> + - const: mac >>> + - const: phy >>> + >>> + hisilicon,phy-reset-delays-us: >>> + minItems: 3 >>> + maxItems: 3 >>> + description: | >>> + The 1st cell is reset pre-delay in micro seconds. >>> + The 2nd cell is reset pulse in micro seconds. >>> + The 3rd cell is reset post-delay in micro seconds. >> items: >> - description: >> >> Anyway, isn't this property of the phy? > It ought to be. But it seems a bit hard to implement it like this. Why? You have phy node, so phy should know what to do. Best regards, Krzysztof
On 2/16/2024 5:41 PM, Krzysztof Kozlowski wrote: > On 16/02/2024 10:36, Yang Xiwen wrote: >>>> + maxItems: 2 >>>> + >>>> + reset-names: >>>> + items: >>>> + - const: mac >>>> + - const: phy >>>> + >>>> + hisilicon,phy-reset-delays-us: >>>> + minItems: 3 >>>> + maxItems: 3 >>>> + description: | >>>> + The 1st cell is reset pre-delay in micro seconds. >>>> + The 2nd cell is reset pulse in micro seconds. >>>> + The 3rd cell is reset post-delay in micro seconds. >>> items: >>> - description: >>> >>> Anyway, isn't this property of the phy? >> It ought to be. But it seems a bit hard to implement it like this. > Why? You have phy node, so phy should know what to do. It's not PHY which needs special treatment. It's the MAC. The PHY needs to be reset with MAC and BUS clocks disabled explicitly(see hisi_femac_phy_reset() in patch 1). I can't find a way to implement this easily except moving all clocks/resets management to MAC driver. Especially when the boot loader might has enabled the clocks already (so the clocks need to be disabled explicitly(i.e. call clk_prepare_enable() and clk_disable() for them, and ensure there is only one consumer). > > > > Best regards, > Krzysztof >
> + femac: ethernet@9c30000 { > + compatible = "hisilicon,hi3798mv200-femac"; > + reg = <0x9c30000 0x1000>, <0x9c31300 0x200>; > + ranges = <0x0 0x9c30000 0x10000>; > + #address-cells = <1>; > + #size-cells = <1>; > + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&crg HISTB_ETH0_MAC_CLK>, > + <&crg HISTB_ETH0_MACIF_CLK>, > + <&crg HISTB_ETH0_PHY_CLK>; > + clock-names = "mac", "macif", "phy"; > + resets = <&crg 0xd0 3>, <&crg 0x388 4>; > + reset-names = "mac", "phy"; > + phy-handle = <&fephy>; > + phy-connection-type = "mii"; > + // To be filled by bootloader > + mac-address = [00 00 00 00 00 00]; > + hisilicon,phy-reset-delays-us = <10000 10000 500000>; > + status = "okay"; > + > + mdio: mdio@1100 { > + compatible = "hisilicon,hisi-femac-mdio"; Is the MDIO bus master a device of its own? Is this compatible actually used anywhere? There are generally two different ways an MDIO bus master works. It is an individual device, with its own register space and it gets probed as an independent device. In this case, it needs a compatible to indicate what driver should be used. Or the MDIO bus master is embedded within a MAC driver. It shares the register space with the MAC driver. It is not a device which gets probed, and so it does not need a compatible. The MAC drivers compatible is sufficient. Andrew
On 2/16/2024 9:11 PM, Andrew Lunn wrote: >> + femac: ethernet@9c30000 { >> + compatible = "hisilicon,hi3798mv200-femac"; >> + reg = <0x9c30000 0x1000>, <0x9c31300 0x200>; >> + ranges = <0x0 0x9c30000 0x10000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&crg HISTB_ETH0_MAC_CLK>, >> + <&crg HISTB_ETH0_MACIF_CLK>, >> + <&crg HISTB_ETH0_PHY_CLK>; >> + clock-names = "mac", "macif", "phy"; >> + resets = <&crg 0xd0 3>, <&crg 0x388 4>; >> + reset-names = "mac", "phy"; >> + phy-handle = <&fephy>; >> + phy-connection-type = "mii"; >> + // To be filled by bootloader >> + mac-address = [00 00 00 00 00 00]; >> + hisilicon,phy-reset-delays-us = <10000 10000 500000>; >> + status = "okay"; >> + >> + mdio: mdio@1100 { >> + compatible = "hisilicon,hisi-femac-mdio"; > Is the MDIO bus master a device of its own? Is this compatible > actually used anywhere? > > There are generally two different ways an MDIO bus master works. It is > an individual device, with its own register space and it gets probed > as an independent device. In this case, it needs a compatible to > indicate what driver should be used. > > Or the MDIO bus master is embedded within a MAC driver. It shares the > register space with the MAC driver. It is not a device which gets > probed, and so it does not need a compatible. The MAC drivers > compatible is sufficient. I guess this is the main difference between the old "hi3516dv300-femac" and the new "hi3798mv200-femac". The old binding says there are individual clocks for MDIO bus and MAC for hi3516. But according to my test, it's not true for hi3798mv200. I've tried accessing MDIO address space and MAC controller address space in u-boot with `md` and `mw` [1]. From the result, i guess the CLK_BUS is the System Bus clock (AHB Bus clock), and the CLK_MAC is the clock shared by both MDIO bus and MAC. The MAC has a internal clock divider to divide the input clock(54MHz in common) to a configurable variable rate. Due to the fact that MDIO bus address space is inside MAC address space ( MAC is at `f9c30000- f9c40000`, MDIO bus is at `f9c31100-f9c31120` ). The only thing i can tell it's inside the SoC, but i can't say it's 100% completely integrated to the MAC controller, though highly possible. [1]: the result is summarized below, `md f9c31300` in u-boot is used to poke the register values: CLK_BUS | CLK_MAC | register values Off | Off | All zero Off | On | All zero On | Off | System Hangs On | On | All okay > > Andrew
> I've tried accessing MDIO address space and MAC controller address space in > u-boot with `md` and `mw` [1]. From the result, i guess the CLK_BUS is the > System Bus clock (AHB Bus clock), and the CLK_MAC is the clock shared by > both MDIO bus and MAC. The MAC has a internal clock divider to divide the > input clock(54MHz in common) to a configurable variable rate. In general, sharing a clock is not a problem. The clock API does reference counting. So if two consumers enable the clock, it will not be disabled until two consumes disable the clock. So it should not be an issue for both the MAC and the MDIO driver to consume the clock. However, the funny PHY reset code is going to be key here. We need to understand that in more detail. Talking about details, you commit messages need improving. The commit message is your chance to answer all the reviewers questions before they even ask them. Removing a binding was always going to need justification, so you needed to have that in the commit message. In order to review a DT bindings, having an overview of what the hardware actually looks like is needed. So that is something which you can add to the commit messages. Please take a look at your patches from the perspective of a reviewer, somebody how knows nothing about this device. What information is needed to understand the patches? Andrew
On 2/16/2024 10:10 PM, Andrew Lunn wrote: >> I've tried accessing MDIO address space and MAC controller address space in >> u-boot with `md` and `mw` [1]. From the result, i guess the CLK_BUS is the >> System Bus clock (AHB Bus clock), and the CLK_MAC is the clock shared by >> both MDIO bus and MAC. The MAC has a internal clock divider to divide the >> input clock(54MHz in common) to a configurable variable rate. > In general, sharing a clock is not a problem. The clock API does > reference counting. So if two consumers enable the clock, it will not > be disabled until two consumes disable the clock. So it should not be > an issue for both the MAC and the MDIO driver to consume the clock. > > However, the funny PHY reset code is going to be key here. We need to > understand that in more detail. I don't know about details too much, either. All the resources i have is a brief TRM and the downstream linux kernel code[1], U-Boot code[2]. The idea of managing all clocks and resets in MAC driver is taken from hix5hd2_gmac.c(in the same directory). > > Talking about details, you commit messages need improving. The commit > message is your chance to answer all the reviewers questions before > they even ask them. Removing a binding was always going to need > justification, so you needed to have that in the commit message. In > order to review a DT bindings, having an overview of what the hardware > actually looks like is needed. So that is something which you can add > to the commit messages. Thanks for your comment. Also sorry for the inconvenience I brought. > > Please take a look at your patches from the perspective of a reviewer, > somebody how knows nothing about this device. What information is > needed to understand the patches? Will rewrite commit logs in next version. > > Andrew [1]: https://github.com/JasonFreeLab/HiSTBLinuxV100R005C00SPC050/blob/fd20f78ab02934e71474dbb1d933c6ec911b01c9/source/kernel/linux-4.4.y/drivers/net/ethernet/hieth/hieth.c#L1281 [2]: https://github.com/JasonFreeLab/HiSTBLinuxV100R005C00SPC050/blob/fd20f78ab02934e71474dbb1d933c6ec911b01c9/source/boot/fastboot/drivers/net/hisfv300/sys.c#L50
diff --git a/Documentation/devicetree/bindings/net/hisilicon-femac.yaml b/Documentation/devicetree/bindings/net/hisilicon-femac.yaml new file mode 100644 index 000000000000..008127e148aa --- /dev/null +++ b/Documentation/devicetree/bindings/net/hisilicon-femac.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/hisilicon-femac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Fast Ethernet MAC controller + +maintainers: + - Yang Xiwen <forbidden405@foxmail.com> + +allOf: + - $ref: ethernet-controller.yaml + +properties: + compatible: + enum: + - hisilicon,hi3798mv200-femac + + reg: + minItems: 2 + maxItems: 2 + description: | + The first region is the MAC core register base and size. + The second region is the global MAC control register. + + ranges: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: mac + - const: macif + - const: phy + + resets: + minItems: 2 + maxItems: 2 + + reset-names: + items: + - const: mac + - const: phy + + hisilicon,phy-reset-delays-us: + minItems: 3 + maxItems: 3 + description: | + The 1st cell is reset pre-delay in micro seconds. + The 2nd cell is reset pulse in micro seconds. + The 3rd cell is reset post-delay in micro seconds. + +patternProperties: + '^mdio@[0-9a-f]+$': + type: object + description: See ./hisi-femac-mdio.txt + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - phy-connection-type + - phy-handle + - hisilicon,phy-reset-delays-us + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/histb-clock.h> + + #ifndef HISTB_ETH0_PHY_CLK + #define HISTB_ETH0_PHY_CLK 0 + #endif + femac: ethernet@9c30000 { + compatible = "hisilicon,hi3798mv200-femac"; + reg = <0x9c30000 0x1000>, <0x9c31300 0x200>; + ranges = <0x0 0x9c30000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_ETH0_MAC_CLK>, + <&crg HISTB_ETH0_MACIF_CLK>, + <&crg HISTB_ETH0_PHY_CLK>; + clock-names = "mac", "macif", "phy"; + resets = <&crg 0xd0 3>, <&crg 0x388 4>; + reset-names = "mac", "phy"; + phy-handle = <&fephy>; + phy-connection-type = "mii"; + // To be filled by bootloader + mac-address = [00 00 00 00 00 00]; + hisilicon,phy-reset-delays-us = <10000 10000 500000>; + status = "okay"; + + mdio: mdio@1100 { + compatible = "hisilicon,hisi-femac-mdio"; + reg = <0x1100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + fephy: ethernet-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + };