From patchwork Fri Mar 1 10:42:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= X-Patchwork-Id: 13578310 X-Patchwork-Delegate: kuba@kernel.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 288DE20B29; Fri, 1 Mar 2024 10:42:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709289779; cv=none; b=JMs48myouFoLzuIv/2W/aEWg8pw/8vZxaW8Rw4h8Fx+izI+m4R5C0t8NcddrYXFr1Sx4al8mxMy7RBz1vHN9wXFfQcZKnaan3FZ3/cGJang8GrteRwWplOwUBO1VWZGr5rTz2hRT4QbjFrtcoIwaMNaOAzah8EHx0GjQUjCOYnU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709289779; c=relaxed/simple; bh=wUpyw43HcHACBQ/8AUAV0rAR4ahB+zKQE8l7LVuV9Hs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DiEk8RcVEhrnTO0qfq25lPtZtrw0n5hBkyZP3+blUcolMx4LU8YPHasq7Jjyv6UCqEXH/eM3bmqmkP6ilEFR3N4UgDHEevf/1+DfALb+fxSZbRVvbPlveAI/6XoH4t8yji2W73rTZuzAL32plhKMpPFcdSTATxyj9RLTZYHvqCw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Kcz6v5q7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Kcz6v5q7" Received: by smtp.kernel.org (Postfix) with ESMTPS id DD65DC433A6; Fri, 1 Mar 2024 10:42:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1709289778; bh=wUpyw43HcHACBQ/8AUAV0rAR4ahB+zKQE8l7LVuV9Hs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Kcz6v5q7MMQfEEkzl/ykwxZ+ENVTtozqoGi5h9AiOT9Pix2I0OeWyL9AYgxRRxw+h 51Lmfkx/wCQbGuuvSIVv7Nb02WGATTe6mFnfI9CS0/2PnrnABUi5II/BvjOpzkr9zv qHQpxKGFEQxHLfpldcbfhdOtg+P+sXFKIHcUdHsVMoFwLlANitHe5JYVezWSxLmWwa b9jksH9thiopFLwLBkMMxuFRJtnC3GV85nFf4qOGdGjjkLs7Ld/886YON2+es/aYKr xWiUeY1aGWIBZ+Dt0J6YJ/e0IPmZx7KstidKZINX/syjmEkaNKuxPmwQZ6g3VpXlov lQJsopR/CEunQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3B85C54E41; Fri, 1 Mar 2024 10:42:58 +0000 (UTC) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= via B4 Relay Date: Fri, 01 Mar 2024 12:42:59 +0200 Subject: [PATCH net-next v3 3/9] net: dsa: mt7530: do not use SW_PHY_RST to reset MT7531 switch Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240301-for-netnext-mt7530-improvements-3-v3-3-449f4f166454@arinc9.com> References: <20240301-for-netnext-mt7530-improvements-3-v3-0-449f4f166454@arinc9.com> In-Reply-To: <20240301-for-netnext-mt7530-improvements-3-v3-0-449f4f166454@arinc9.com> To: Daniel Golle , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: mithat.guner@xeront.com, erkin.bozoglu@xeront.com, Bartel Eerdekens , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1709289776; l=1298; i=arinc.unal@arinc9.com; s=arinc9-Xeront; h=from:subject:message-id; bh=ecurYkRWOTqqGU2AKHni4Fzup3XR61+gzZ3STlqM5Z4=; b=EcZZqAw0Px2l53CBDBN+OKBDR6BvhuwtATODCOqg0mePBSm4mjtM0F/hIs6zkpLPjTmfUVOAw G8CgcELxzmeB3sKfMJqHSwGicDtnlFN/3Ff4mY6SeGKl4qPnLVboMNF X-Developer-Key: i=arinc.unal@arinc9.com; a=ed25519; pk=z49tLn29CyiL4uwBTrqH9HO1Wu3sZIuRp4DaLZvtP9M= X-Endpoint-Received: by B4 Relay for arinc.unal@arinc9.com/arinc9-Xeront with auth_id=137 X-Original-From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= Reply-To: X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL According to the document MT7531 Reference Manual for Development Board v1.0, the SW_PHY_RST bit on the SYS_CTRL register doesn't exist for MT7531. This is likely why forcing link down on all ports is necessary for MT7531. Therefore, do not set SW_PHY_RST on mt7531_setup(). Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 5cfd303b773f..296711fd5c43 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2451,14 +2451,12 @@ mt7531_setup(struct dsa_switch *ds) val = mt7530_read(priv, MT7531_TOP_SIG_SR); priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); - /* all MACs must be forced link-down before sw reset */ + /* Force link down on all ports before internal reset */ for (i = 0; i < MT7530_NUM_PORTS; i++) mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); /* Reset the switch through internal reset */ - mt7530_write(priv, MT7530_SYS_CTRL, - SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | - SYS_CTRL_REG_RST); + mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); if (!priv->p5_sgmii) { mt7531_pll_setup(priv);