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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Chester Lin , =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger , NXP S32 Linux Team , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Michael Turquette , Stephen Boyd , Richard Cochran , Andrew Halaney , Simon Horman , Bartosz Golaszewski , Johannes Zink , Shenwei Wang , "Russell King (Oracle)" , Swee Leong Ching , Giuseppe Cavallaro , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-clk@vger.kernel.org Subject: [PATCH 3/3] dt-bindings: net: add schema for NXP S32 dwmac glue driver Date: Fri, 15 Mar 2024 23:27:49 +0100 Message-Id: <20240315222754.22366-4-wafgo01@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240315222754.22366-1-wafgo01@gmail.com> References: <20240315222754.22366-1-wafgo01@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Add DT binding schema documentation for the NXP S32 dwmac glue driver. This documentation is based on the patchset originally provided by Chester Lin [1]. This commit is a re-send of [2] and [3]. [1] https://patchwork.kernel.org/project/netdevbpf/patch/20221031101052.14956-6-clin@suse.com/#25068228 [2] https://lore.kernel.org/lkml/20221031101052.14956-1-clin@suse.com/T/#me96c28bd0536de276dee941469ea084d51b42244 [3] https://lore.kernel.org/lkml/20221031101052.14956-1-clin@suse.com/T/#m887a1b34e612f8dc0d5b718e4d6834c083f1e245 Signed-off-by: Wadim Mueller --- .../bindings/net/nxp,s32-dwmac.yaml | 130 ++++++++++++++++++ .../devicetree/bindings/net/snps,dwmac.yaml | 5 +- 2 files changed, 133 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml new file mode 100644 index 000000000000..0fbca6ce7d60 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NXP S32 DWMAC Ethernet controller + +select: + properties: + compatible: + contains: + enum: + - nxp,s32-dwmac + required: + - compatible + +allOf: + - $ref: "snps,dwmac.yaml#" + +properties: + compatible: + contains: + enum: + - nxp,s32-dwmac + + reg: + items: + - description: Main GMAC registers + - description: S32 MAC control registers + + dma-coherent: + description: + Declares GMAC device as DMA coherent + + clocks: + items: + - description: Main GMAC clock + - description: Peripheral registers clock + - description: Transmit SGMII clock + - description: Transmit RGMII clock + - description: Transmit RMII clock + - description: Transmit MII clock + - description: Receive SGMII clock + - description: Receive RGMII clock + - description: Receive RMII clock + - description: Receive MII clock + - description: + PTP reference clock. This clock is used for programming the + Timestamp Addend Register. If not passed then the system + clock will be used. + + clock-names: + items: + - const: stmmaceth + - const: pclk + - const: tx_sgmii + - const: tx_rgmii + - const: tx_rmii + - const: tx_mii + - const: rx_sgmii + - const: rx_rgmii + - const: rx_rmii + - const: rx_mii + - const: ptp_ref + + tx-fifo-depth: + const: 20480 + + rx-fifo-depth: + const: 20480 + +required: + - compatible + - reg + - tx-fifo-depth + - rx-fifo-depth + - clocks + - clock-names + +additionalProperties: true + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + gmac0: ethernet@4033c000 { + compatible = "nxp,s32-dwmac"; + reg = <0x4033c000 0x2000>, /* gmac IP */ + <0x4007C004 0x4>; /* S32 CTRL_STS reg */ + interrupt-parent = <&gic>; + interrupts = ; + interrupt-names = "macirq"; + phy-mode = "rgmii-id"; + tx-fifo-depth = <20480>; + rx-fifo-depth = <20480>; + dma-coherent; + clocks = <&clks S32_SCMI_CLK_GMAC0_AXI>, + <&clks S32_SCMI_CLK_GMAC0_AXI>, + <&clks S32_SCMI_CLK_GMAC0_TX_SGMII>, + <&clks S32_SCMI_CLK_GMAC0_TX_RGMII>, + <&clks S32_SCMI_CLK_GMAC0_TX_RMII>, + <&clks S32_SCMI_CLK_GMAC0_TX_MII>, + <&clks S32_SCMI_CLK_GMAC0_RX_SGMII>, + <&clks S32_SCMI_CLK_GMAC0_RX_RGMII>, + <&clks S32_SCMI_CLK_GMAC0_RX_RMII>, + <&clks S32_SCMI_CLK_GMAC0_RX_MII>, + <&clks S32_SCMI_CLK_GMAC0_TS>; + clock-names = "stmmaceth", "pclk", + "tx_sgmii", "tx_rgmii", "tx_rmii", "tx_mii", + "rx_sgmii", "rx_rgmii", "rx_rmii", "rx_mii", + "ptp_ref"; + + gmac0_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + ethernet-phy@1 { + reg = <0x01>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 5c2769dc689a..e5bf61347b66 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -66,6 +66,7 @@ properties: - ingenic,x2000-mac - loongson,ls2k-dwmac - loongson,ls7a-dwmac + - nxp,s32-dwmac - qcom,qcs404-ethqos - qcom,sa8775p-ethqos - qcom,sc8280xp-ethqos @@ -117,7 +118,7 @@ properties: clocks: minItems: 1 - maxItems: 8 + maxItems: 11 additionalItems: true items: - description: GMAC main clock @@ -129,7 +130,7 @@ properties: clock-names: minItems: 1 - maxItems: 8 + maxItems: 11 additionalItems: true contains: enum: