| Message ID | 20240326052720.4441-1-hkelam@marvell.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 40d4b4807cadd83fb3f46cc8cd67a945b5b25461 |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [net] Octeontx2-af: fix pause frame configuration in GMP mode | expand |
On Tue, Mar 26, 2024 at 10:57:20AM +0530, Hariprasad Kelam wrote: > The Octeontx2 MAC block (CGX) has separate data paths (SMU and GMP) for > different speeds, allowing for efficient data transfer. > > The previous patch which added pause frame configuration has a bug due > to which pause frame feature is not working in GMP mode. > > This patch fixes the issue by configurating appropriate registers. > > Fixes: f7e086e754fe ("octeontx2-af: Pause frame configuration at cgx") > Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> nit: For consistency with git history, octeontx2-af should be all lowercase in the subject Reviewed-by: Simon Horman <horms@kernel.org>
Hello: This patch was applied to netdev/net.git (main) by Paolo Abeni <pabeni@redhat.com>: On Tue, 26 Mar 2024 10:57:20 +0530 you wrote: > The Octeontx2 MAC block (CGX) has separate data paths (SMU and GMP) for > different speeds, allowing for efficient data transfer. > > The previous patch which added pause frame configuration has a bug due > to which pause frame feature is not working in GMP mode. > > This patch fixes the issue by configurating appropriate registers. > > [...] Here is the summary with links: - [net] Octeontx2-af: fix pause frame configuration in GMP mode https://git.kernel.org/netdev/net/c/40d4b4807cad You are awesome, thank you!
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c index 3c0f55b3e48e..b86f3224f0b7 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c @@ -808,6 +808,11 @@ static int cgx_lmac_enadis_pause_frm(void *cgxd, int lmac_id, if (!is_lmac_valid(cgx, lmac_id)) return -ENODEV; + cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); + cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; + cfg |= rx_pause ? CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK : 0x0; + cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); + cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; cfg |= rx_pause ? CGX_SMUX_RX_FRM_CTL_CTL_BCK : 0x0;
The Octeontx2 MAC block (CGX) has separate data paths (SMU and GMP) for different speeds, allowing for efficient data transfer. The previous patch which added pause frame configuration has a bug due to which pause frame feature is not working in GMP mode. This patch fixes the issue by configurating appropriate registers. Fixes: f7e086e754fe ("octeontx2-af: Pause frame configuration at cgx") Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> --- drivers/net/ethernet/marvell/octeontx2/af/cgx.c | 5 +++++ 1 file changed, 5 insertions(+)