From patchwork Tue Apr 9 08:18:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksij Rempel X-Patchwork-Id: 13621986 X-Patchwork-Delegate: kuba@kernel.org Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83FF87E59F for ; Tue, 9 Apr 2024 08:19:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712650743; cv=none; b=rJXj4PsXj0uIgn19pVV+ULIYjG+wM3w7b0yPKTwAgXz1bPvfjkGa3wkU9YrDlnxQn8EkrYU5t4UFpbMimmpK7KN2CvnqwGlF9fSfggkvKTebFVyP8LwsdJAfd7f81YY0FAev5Kj6kbfe/I0G79Noq3wwEYosD9RXbA38+FFWjHg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712650743; c=relaxed/simple; bh=UbJm4CAN9/EAj1i27GEuzt2Qj9RP8AyisQ+CWSykUA0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jGFYjwy8qFAdLQbQR4wqIvtYmqrZ8LyHZbIVnyi5EGJXaVPd4iexJdxA8uudZ6oKKM8bgzZJGzCp67hROMOm85eXGyTJtXtsIC96feN0r9PiUsSBYvs/+S5HVZvWwTUjeC6/b8kCGgg6ddtuvrhwjn7UjwH3b/43jTCfZyUz2Fk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1ru6gw-0006VI-Nj; Tue, 09 Apr 2024 10:18:54 +0200 Received: from [2a0a:edc0:0:1101:1d::ac] (helo=dude04.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ru6gu-00BGpP-Me; Tue, 09 Apr 2024 10:18:52 +0200 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1ru6gu-00EoUk-20; Tue, 09 Apr 2024 10:18:52 +0200 From: Oleksij Rempel To: "David S. Miller" , Andrew Lunn , Eric Dumazet , Florian Fainelli , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Woojung Huh , Arun Ramadoss Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, UNGLinuxDriver@microchip.com, David Ahern , Simon Horman , Willem de Bruijn , =?utf-8?q?S=C3=B8ren_Andersen?= Subject: [PATCH net-next v5 2/9] net: dsa: microchip: add IPV information support Date: Tue, 9 Apr 2024 10:18:44 +0200 Message-Id: <20240409081851.3530641-3-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240409081851.3530641-1-o.rempel@pengutronix.de> References: <20240409081851.3530641-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Most of Microchip KSZ switches use Internal Priority Value associated with every frame. For example, it is possible to map any VLAN PCP or DSCP value to IPV and at the end, map IPV to a queue. Since amount of IPVs is not equal to amount of queues, add this information and make use of it in some functions. Signed-off-by: Oleksij Rempel Acked-by: Arun Ramadoss --- changes v3: - rename max_ipvs to num_ipvs - drop comparison of num_tx_queues and num_ipvs. It makes no much sense. --- drivers/net/dsa/microchip/ksz_common.c | 21 +++++++++++++++++++-- drivers/net/dsa/microchip/ksz_common.h | 2 +- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c index 42330e8fd26e7..b2d1c61400c51 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -1194,6 +1194,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 3, /* total port count */ .port_nirqs = 3, .num_tx_queues = 4, + .num_ipvs = 8, .tc_cbs_supported = true, .tc_ets_supported = true, .ops = &ksz9477_dev_ops, @@ -1223,6 +1224,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .cpu_ports = 0x10, /* can be configured as cpu port */ .port_cnt = 5, /* total cpu and user ports */ .num_tx_queues = 4, + .num_ipvs = 4, .ops = &ksz8_dev_ops, .ksz87xx_eee_link_erratum = true, .mib_names = ksz9477_mib_names, @@ -1262,6 +1264,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .cpu_ports = 0x10, /* can be configured as cpu port */ .port_cnt = 5, /* total cpu and user ports */ .num_tx_queues = 4, + .num_ipvs = 4, .ops = &ksz8_dev_ops, .ksz87xx_eee_link_erratum = true, .mib_names = ksz9477_mib_names, @@ -1287,6 +1290,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .cpu_ports = 0x10, /* can be configured as cpu port */ .port_cnt = 5, /* total cpu and user ports */ .num_tx_queues = 4, + .num_ipvs = 4, .ops = &ksz8_dev_ops, .ksz87xx_eee_link_erratum = true, .mib_names = ksz9477_mib_names, @@ -1312,6 +1316,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .cpu_ports = 0x4, /* can be configured as cpu port */ .port_cnt = 3, .num_tx_queues = 4, + .num_ipvs = 4, .ops = &ksz8_dev_ops, .mib_names = ksz88xx_mib_names, .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), @@ -1336,6 +1341,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 7, /* total physical port count */ .port_nirqs = 4, .num_tx_queues = 4, + .num_ipvs = 8, .tc_cbs_supported = true, .tc_ets_supported = true, .ops = &ksz9477_dev_ops, @@ -1370,6 +1376,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 6, /* total physical port count */ .port_nirqs = 2, .num_tx_queues = 4, + .num_ipvs = 8, .ops = &ksz9477_dev_ops, .mib_names = ksz9477_mib_names, .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), @@ -1402,6 +1409,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 7, /* total physical port count */ .port_nirqs = 2, .num_tx_queues = 4, + .num_ipvs = 8, .ops = &ksz9477_dev_ops, .mib_names = ksz9477_mib_names, .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), @@ -1432,6 +1440,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 3, /* total port count */ .port_nirqs = 2, .num_tx_queues = 4, + .num_ipvs = 8, .ops = &ksz9477_dev_ops, .mib_names = ksz9477_mib_names, .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), @@ -1458,6 +1467,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 3, /* total port count */ .port_nirqs = 3, .num_tx_queues = 4, + .num_ipvs = 8, .tc_cbs_supported = true, .tc_ets_supported = true, .ops = &ksz9477_dev_ops, @@ -1486,6 +1496,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 7, /* total port count */ .port_nirqs = 3, .num_tx_queues = 4, + .num_ipvs = 8, .tc_cbs_supported = true, .tc_ets_supported = true, .ops = &ksz9477_dev_ops, @@ -1519,6 +1530,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 7, /* total physical port count */ .port_nirqs = 3, .num_tx_queues = 4, + .num_ipvs = 8, .tc_cbs_supported = true, .tc_ets_supported = true, .ops = &ksz9477_dev_ops, @@ -1551,6 +1563,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 5, /* total physical port count */ .port_nirqs = 6, .num_tx_queues = 8, + .num_ipvs = 8, .tc_cbs_supported = true, .tc_ets_supported = true, .ops = &lan937x_dev_ops, @@ -1578,6 +1591,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 6, /* total physical port count */ .port_nirqs = 6, .num_tx_queues = 8, + .num_ipvs = 8, .tc_cbs_supported = true, .tc_ets_supported = true, .ops = &lan937x_dev_ops, @@ -1605,6 +1619,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 8, /* total physical port count */ .port_nirqs = 6, .num_tx_queues = 8, + .num_ipvs = 8, .tc_cbs_supported = true, .tc_ets_supported = true, .ops = &lan937x_dev_ops, @@ -1636,6 +1651,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 5, /* total physical port count */ .port_nirqs = 6, .num_tx_queues = 8, + .num_ipvs = 8, .tc_cbs_supported = true, .tc_ets_supported = true, .ops = &lan937x_dev_ops, @@ -1667,6 +1683,7 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 8, /* total physical port count */ .port_nirqs = 6, .num_tx_queues = 8, + .num_ipvs = 8, .tc_cbs_supported = true, .tc_ets_supported = true, .ops = &lan937x_dev_ops, @@ -3522,7 +3539,7 @@ static int ksz_tc_ets_add(struct ksz_device *dev, int port, for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { int queue; - if (tc_prio > KSZ9477_MAX_TC_PRIO) + if (tc_prio >= dev->info->num_ipvs) break; queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); @@ -3564,7 +3581,7 @@ static int ksz_tc_ets_del(struct ksz_device *dev, int port) /* Revert the queue mapping for TC-priority to its default setting on * the chip. */ - for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) { + for (tc_prio = 0; tc_prio < dev->info->num_ipvs; tc_prio++) { int queue; queue = tc_prio >> s; diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h index 40c11b0d6b625..900e9ac06d013 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -58,6 +58,7 @@ struct ksz_chip_data { int port_cnt; u8 port_nirqs; u8 num_tx_queues; + u8 num_ipvs; /* number of Internal Priority Values */ bool tc_cbs_supported; bool tc_ets_supported; const struct ksz_dev_ops *ops; @@ -722,7 +723,6 @@ static inline int is_lan937x(struct ksz_device *dev) #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 #define KSZ9477_PORT_TC_MAP_S 4 -#define KSZ9477_MAX_TC_PRIO 7 /* CBS related registers */ #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900