From patchwork Fri Apr 12 06:57:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi-De Wu X-Patchwork-Id: 13626974 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FC7E502B8; Fri, 12 Apr 2024 06:57:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712905082; cv=none; b=Dt4ag8CflyO7hxNhtaBUjQUjxykvwEZ4VRH5eeZINWCSSjx4QH3GXrWUoKVkW9cuZnYI4XSn3YQz6vqm7cKsMo/MwEJ7qcjl3e9KRbyib1wHEvI5HWbc7J/BinkVjyMNNfN4MGWDYwLdbJF+HZdo+D1H7LoNaIyb+AWqhm1Skxo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712905082; c=relaxed/simple; bh=6NZSClo6H6e3G+90fKqbClcpzseP+wjt3nV7iazfOL4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OFeKcNoCy7EHJcNRMjE6KUJkMgN9q+431A++18/XADEzwU1T1l0N+bfv9MmQwU6q2YDWBeVsZGrin1KPNgyqVRbnfClw53L7qTFzOoBTC2vqh0mgWLZS3+SmTgsJYxx0IgMiqA3lPkUpAhJw5p4p6BhM6dwa4r28hPswckEP5R4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=N53HGuQv; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="N53HGuQv" X-UUID: f9ba49fcf89911eeb8927bc1f75efef4-20240412 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=cANxux1/htpGt52y+Aeho8J1w0VjkDggLi2Ws4XYndE=; b=N53HGuQvVMK+LRhWwTTclNt75yZT2DWWbxmhYZ9/GfMJIMG7XK979gXNiWmS6TaCt6uXjSnjYcGqylaQIKvKMx9TfNJOMsP2lCt1tYa3KekGU97DxyCjNFT8qLGRC22m/D/t5RC/hZ7KIlJY/fKnvOxpV/p1v7JgAUo/eCWblM0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:8c7f5101-f476-489b-b76b-a8faf39e4798,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:6f543d0,CLOUDID:8c9a7e91-e2c0-40b0-a8fe-7c7e47299109,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: f9ba49fcf89911eeb8927bc1f75efef4-20240412 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 213153288; Fri, 12 Apr 2024 14:57:49 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 12 Apr 2024 14:57:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 12 Apr 2024 14:57:48 +0800 From: Yi-De Wu To: Yingshiuan Pan , Ze-Yu Wang , Yi-De Wu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Catalin Marinas , Will Deacon , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , , David Bradil , Trilok Soni , My Chuang , Shawn Hsiao , PeiLun Suei , Liju Chen , Willix Yeh , Kevenny Hsieh Subject: [PATCH v10 21/21] virt: geniezone: Enable PTP for synchronizing time between host and guest VMs Date: Fri, 12 Apr 2024 14:57:18 +0800 Message-ID: <20240412065718.29105-22-yi-de.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240412065718.29105-1-yi-de.wu@mediatek.com> References: <20240412065718.29105-1-yi-de.wu@mediatek.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: "Kevenny Hsieh" Enabled Precision Time Protocol (PTP) for improved host-guest VM time synchronization, optimizing operations needing precise clock sync in virtual environment. Signed-off-by: Kevenny Hsieh Signed-off-by: Liju Chen Signed-off-by: Yi-De Wu --- arch/arm64/geniezone/Makefile | 2 +- arch/arm64/geniezone/gzvm_arch_common.h | 3 + arch/arm64/geniezone/hvc.c | 73 +++++++++++++++++++++++++ drivers/virt/geniezone/gzvm_exception.c | 3 +- include/linux/soc/mediatek/gzvm_drv.h | 1 + include/uapi/linux/gzvm.h | 1 + 6 files changed, 80 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/geniezone/hvc.c diff --git a/arch/arm64/geniezone/Makefile b/arch/arm64/geniezone/Makefile index 0e4f1087f9de..553a64a926dc 100644 --- a/arch/arm64/geniezone/Makefile +++ b/arch/arm64/geniezone/Makefile @@ -4,6 +4,6 @@ # include $(srctree)/drivers/virt/geniezone/Makefile -gzvm-y += vm.o vcpu.o vgic.o +gzvm-y += vm.o vcpu.o vgic.o hvc.o obj-$(CONFIG_MTK_GZVM) += gzvm.o diff --git a/arch/arm64/geniezone/gzvm_arch_common.h b/arch/arm64/geniezone/gzvm_arch_common.h index 192d023722e5..8f5d8528ab96 100644 --- a/arch/arm64/geniezone/gzvm_arch_common.h +++ b/arch/arm64/geniezone/gzvm_arch_common.h @@ -83,6 +83,8 @@ int gzvm_hypcall_wrapper(unsigned long a0, unsigned long a1, * @__pad: add an explicit '__u32 __pad;' in the middle to make it clear * what the actual layout is. * @lr: The array of LRs(list registers). + * @vtimer_offset: The offset maintained by hypervisor that is host cycle count + * when guest VM startup. * * - Keep the same layout of hypervisor data struct. * - Sync list registers back for acking virtual device interrupt status. @@ -91,6 +93,7 @@ struct gzvm_vcpu_hwstate { __le32 nr_lrs; __le32 __pad; __le64 lr[GIC_V3_NR_LRS]; + __le64 vtimer_offset; }; static inline unsigned int diff --git a/arch/arm64/geniezone/hvc.c b/arch/arm64/geniezone/hvc.c new file mode 100644 index 000000000000..3d7f71f20dce --- /dev/null +++ b/arch/arm64/geniezone/hvc.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + */ +#include +#include +#include +#include +#include "gzvm_arch_common.h" + +#define GZVM_PTP_VIRT_COUNTER 0 +#define GZVM_PTP_PHYS_COUNTER 1 +/** + * gzvm_handle_ptp_time() - Sync time between host and guest VM + * @vcpu: Pointer to struct gzvm_vcpu_run in userspace + * @counter: Counter type from guest VM + * Return: Always return 0 because there are no cases of failure + * + * The following register values will be passed to the guest VM + * for time synchronization: + * regs->x0 (upper 32 bits) wall clock time + * regs->x1 (lower 32 bits) wall clock time + * regs->x2 (upper 32 bits) cycles + * regs->x3 (lower 32 bits) cycles + */ +static int gzvm_handle_ptp_time(struct gzvm_vcpu *vcpu, int counter) +{ + struct system_time_snapshot snapshot; + u64 cycles = 0; + + ktime_get_snapshot(&snapshot); + + switch (counter) { + case GZVM_PTP_VIRT_COUNTER: + cycles = snapshot.cycles - + le64_to_cpu(vcpu->hwstate->vtimer_offset); + break; + case GZVM_PTP_PHYS_COUNTER: + cycles = snapshot.cycles; + break; + default: + break; + } + + vcpu->run->hypercall.args[0] = upper_32_bits(snapshot.real); + vcpu->run->hypercall.args[1] = lower_32_bits(snapshot.real); + vcpu->run->hypercall.args[2] = upper_32_bits(cycles); + vcpu->run->hypercall.args[3] = lower_32_bits(cycles); + + return 0; +} + +/** + * gzvm_arch_handle_guest_hvc() - Handle architecture-related guest hvc + * @vcpu: Pointer to struct gzvm_vcpu_run in userspace + * Return: + * * true - This hvc has been processed, no need to back to VMM. + * * false - This hvc has not been processed, require userspace. + */ +bool gzvm_arch_handle_guest_hvc(struct gzvm_vcpu *vcpu) +{ + int ret, counter; + + switch (vcpu->run->hypercall.args[0]) { + case GZVM_HVC_PTP: + counter = vcpu->run->hypercall.args[1]; + ret = gzvm_handle_ptp_time(vcpu, counter); + return (ret == 0) ? true : false; + default: + break; + } + return false; +} diff --git a/drivers/virt/geniezone/gzvm_exception.c b/drivers/virt/geniezone/gzvm_exception.c index 07871ec74651..d824211f49a6 100644 --- a/drivers/virt/geniezone/gzvm_exception.c +++ b/drivers/virt/geniezone/gzvm_exception.c @@ -56,7 +56,6 @@ bool gzvm_handle_guest_hvc(struct gzvm_vcpu *vcpu) ret = gzvm_handle_relinquish(vcpu, ipa); return (ret == 0) ? true : false; default: - break; + return gzvm_arch_handle_guest_hvc(vcpu); } - return false; } diff --git a/include/linux/soc/mediatek/gzvm_drv.h b/include/linux/soc/mediatek/gzvm_drv.h index e123787cd70d..f6b7acca37b8 100644 --- a/include/linux/soc/mediatek/gzvm_drv.h +++ b/include/linux/soc/mediatek/gzvm_drv.h @@ -223,6 +223,7 @@ int gzvm_handle_page_fault(struct gzvm_vcpu *vcpu); bool gzvm_handle_guest_exception(struct gzvm_vcpu *vcpu); int gzvm_handle_relinquish(struct gzvm_vcpu *vcpu, phys_addr_t ipa); bool gzvm_handle_guest_hvc(struct gzvm_vcpu *vcpu); +bool gzvm_arch_handle_guest_hvc(struct gzvm_vcpu *vcpu); int gzvm_arch_create_device(u16 vm_id, struct gzvm_create_device *gzvm_dev); int gzvm_arch_inject_irq(struct gzvm *gzvm, unsigned int vcpu_idx, diff --git a/include/uapi/linux/gzvm.h b/include/uapi/linux/gzvm.h index 5411357ec05e..1cf89213a383 100644 --- a/include/uapi/linux/gzvm.h +++ b/include/uapi/linux/gzvm.h @@ -197,6 +197,7 @@ enum { /* hypercall definitions of GZVM_EXIT_HYPERCALL */ enum { + GZVM_HVC_PTP = 0x86000001, GZVM_HVC_MEM_RELINQUISH = 0xc6000009, };