From patchwork Wed Apr 17 16:39:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karol Kolacinski X-Patchwork-Id: 13633610 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01E44171063 for ; Wed, 17 Apr 2024 16:45:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713372319; cv=none; b=dAkboawT/CJ5BYd33/KgdlBKr14ouugHL1TTwRM+X6Dtl+DUPiFZp/bGtmgMTmQ6zWTOs/lk/G8hNaUd1kxgAg4eYH9TDTH6V/By7BBsRZi1gVXEfuul8aZEmTi7V6rQKwx81Drn494hAdw6mlS27ci9XGt3h93qX4q0uQF+Pco= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713372319; c=relaxed/simple; bh=jvCFIwjD1Qcv6fGgaXN5/haZsfNdU0OBJYXZbFWaHNY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=h3ixS141ReJTTFUZH1MMCDJPH0u7anxGOWaFkpss9dbpIBtJTIp3s6udZWHnuUKCchUUNDyq8McaZKyTIMvMb6keTkmQgXaiv2ZvDaoozkmQI1LfDiKla9j9sbiCBl8OfBcfzizHDBGWNtzRRtbZb+7cppnCwRRUic5Dqdg1kqY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZPvBqC87; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZPvBqC87" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713372318; x=1744908318; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jvCFIwjD1Qcv6fGgaXN5/haZsfNdU0OBJYXZbFWaHNY=; b=ZPvBqC87qMJsfR9K3llSAZ+kihbSU1EGeL0ZUAFIi16/aMv6O5b/t3ix 9GKtKeI3aFjwz21/uEUk/v6gwmVflX/A1zNkVZ5uXq6I+Da9H88kiKV6g 1T34GPkSyiXQ13b4WAj6wSrs7Oc7j2AR7FPaKCa/YZM2NQAIOtUgoUKzn ZgboPtaA07BONl5Oc9eZQZLQl9EfljhPUmxS9meHxyIq3NbOE29RQjC5W /e2lsBBEyWCVcje+mH9adcIyE6YDjEzq6gM6cc77xL/q8WnOixa+n3pOg fwS0422zMpgfgpJvQJMqr/wDfTvuQWyTaw2P68Gl1ZoBKCr2jOH0Zahvs Q==; X-CSE-ConnectionGUID: C0aZppV5RdGl6KqpYrlQ0A== X-CSE-MsgGUID: SbBYCTmtR1OQruKzqvul+w== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="12660739" X-IronPort-AV: E=Sophos;i="6.07,209,1708416000"; d="scan'208";a="12660739" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2024 09:45:18 -0700 X-CSE-ConnectionGUID: ANnHn366TJ2Ne+CT1Zb4xQ== X-CSE-MsgGUID: yRthLLQWQJSh+KLilAwP2w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,209,1708416000"; d="scan'208";a="27470716" Received: from kkolacin-desk1.igk.intel.com ([10.102.102.152]) by orviesa004.jf.intel.com with ESMTP; 17 Apr 2024 09:45:14 -0700 From: Karol Kolacinski To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, Grzegorz Nitka , Prathisna Padmasanan , Pawel Kaminski , Mateusz Polchlopek , Przemek Kitszel , Arkadiusz Kubalewski , Karol Kolacinski Subject: [PATCH v9 iwl-next 10/12] ice: Add NAC Topology device capability parser Date: Wed, 17 Apr 2024 18:39:14 +0200 Message-ID: <20240417164410.850175-24-karol.kolacinski@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240417164410.850175-14-karol.kolacinski@intel.com> References: <20240417164410.850175-14-karol.kolacinski@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Grzegorz Nitka Add new device capability ICE_AQC_CAPS_NAC_TOPOLOGY which allows to determine the mode of operation (1 or 2 NAC). Define a new structure to store data from new capability and corresponding parser code. Co-developed-by: Prathisna Padmasanan Signed-off-by: Prathisna Padmasanan Signed-off-by: Grzegorz Nitka Reviewed-by: Pawel Kaminski Reviewed-by: Mateusz Polchlopek Reviewed-by: Przemek Kitszel Reviewed-by: Arkadiusz Kubalewski Signed-off-by: Karol Kolacinski --- .../net/ethernet/intel/ice/ice_adminq_cmd.h | 2 ++ drivers/net/ethernet/intel/ice/ice_common.c | 31 +++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_type.h | 10 ++++++ 3 files changed, 43 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h index 540c0bdca936..4c125e06310a 100644 --- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h +++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h @@ -121,6 +121,8 @@ struct ice_aqc_list_caps_elem { #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 +#define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085 +#define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087 #define ICE_AQC_CAPS_FW_LAG_SUPPORT 0x0092 #define ICE_AQC_BIT_ROCEV2_LAG 0x01 #define ICE_AQC_BIT_SRIOV_LAG 0x02 diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c index c5473d05698e..d87ad584d77c 100644 --- a/drivers/net/ethernet/intel/ice/ice_common.c +++ b/drivers/net/ethernet/intel/ice/ice_common.c @@ -2583,6 +2583,34 @@ ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, dev_p->supported_sensors); } +/** + * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap + * @hw: pointer to the HW struct + * @dev_p: pointer to device capabilities structure + * @cap: capability element to parse + * + * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. + */ +static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, + struct ice_hw_dev_caps *dev_p, + struct ice_aqc_list_caps_elem *cap) +{ + dev_p->nac_topo.mode = le32_to_cpu(cap->number); + dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; + + dev_info(ice_hw_to_dev(hw), + "PF is configured in %s mode with IP instance ID %d\n", + (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? + "primary" : "secondary", dev_p->nac_topo.id); + + ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", + !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); + ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", + !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); + ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", + dev_p->nac_topo.id); +} + /** * ice_parse_dev_caps - Parse device capabilities * @hw: pointer to the HW struct @@ -2634,6 +2662,9 @@ ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, case ICE_AQC_CAPS_SENSOR_READING: ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); break; + case ICE_AQC_CAPS_NAC_TOPOLOGY: + ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); + break; default: /* Don't list common capabilities as unknown */ if (!found) diff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h index 62ff21b3ee22..f4eb0d03ee4f 100644 --- a/drivers/net/ethernet/intel/ice/ice_type.h +++ b/drivers/net/ethernet/intel/ice/ice_type.h @@ -373,6 +373,15 @@ struct ice_ts_dev_info { u8 ts_ll_int_read; }; +#define ICE_NAC_TOPO_PRIMARY_M BIT(0) +#define ICE_NAC_TOPO_DUAL_M BIT(1) +#define ICE_NAC_TOPO_ID_M GENMASK(0xF, 0) + +struct ice_nac_topology { + u32 mode; + u8 id; +}; + /* Function specific capabilities */ struct ice_hw_func_caps { struct ice_hw_common_caps common_cap; @@ -394,6 +403,7 @@ struct ice_hw_dev_caps { u32 num_flow_director_fltr; /* Number of FD filters available */ struct ice_ts_dev_info ts_dev_info; u32 num_funcs; + struct ice_nac_topology nac_topo; /* bitmap of supported sensors * bit 0 - internal temperature sensor * bit 31:1 - Reserved