From patchwork Mon Apr 22 08:46:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steffen Trumtrar X-Patchwork-Id: 13637988 X-Patchwork-Delegate: kuba@kernel.org Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E1AC4CB55 for ; Mon, 22 Apr 2024 08:46:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713775591; cv=none; b=pCcpcgvw2yy2hkBF/HQcYc7bVgDSegcpN4A7EcnICKNYlpHq2Kl+N56VCJY23fqIqnCyYdDCbycXpBHhfzxRRsj+NAgCp3EqS8V0HgKvahXIqpGI2RinjIzXgz4EuJqQ2mzJAfL2JXoFyHKTRfU3c810xPq5lqWhfxGln636pu8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713775591; c=relaxed/simple; bh=hbWncv3O5p+eXPs67WyDuajeTIZwF1P/8g1gar0nJUo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cbaOAxKSzFrhSgESf+B1tco/6lHScYsJmLY0KJ/HTYAQCc+bjTZQgb007tfX5T10Me38vGNdXglhiEhg3XKVsbS7JNJyMzn9tPCtRPkVUNokVTJFP0ZqP7EhRU+gutvAVe2qkfafr0ij2d0LJfNfzG8hVcctdltyWTUWCOV0UbI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from ptz.office.stw.pengutronix.de ([2a0a:edc0:0:900:1d::77] helo=ratatoskr.trumtrar.info) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1rypJg-0000ML-DO; Mon, 22 Apr 2024 10:46:24 +0200 From: Steffen Trumtrar Date: Mon, 22 Apr 2024 10:46:19 +0200 Subject: [PATCH 3/3] net: stmicro: imx: set TX_CLK direction in RMII mode Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240422-v6-9-topic-imx93-eqos-rmii-v1-3-30151fca43d2@pengutronix.de> References: <20240422-v6-9-topic-imx93-eqos-rmii-v1-0-30151fca43d2@pengutronix.de> In-Reply-To: <20240422-v6-9-topic-imx93-eqos-rmii-v1-0-30151fca43d2@pengutronix.de> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Clark Wang , Linux Team , Alexandre Torgue , Jose Abreu , Maxime Coquelin Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com X-Mailer: b4 0.13.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:900:1d::77 X-SA-Exim-Mail-From: s.trumtrar@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org In case of RMII connection, the TX_CLK must be set to output direction. Parse the register and offset from the devicetree and set the direction of the TX_CLK when the property was provided. Signed-off-by: Steffen Trumtrar --- drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c | 27 +++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c index 6b65420e11b5c..0fc81a626a664 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c @@ -37,6 +37,9 @@ #define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1) #define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) +#define MX93_GPR_ENET_QOS_TX_CLK_SEL_MASK GENMASK(1, 1) +#define MX93_GPR_ENET_QOS_TX_CLK_SEL (0x1 << 1) + #define DMA_BUS_MODE 0x00001000 #define DMA_BUS_MODE_SFT_RESET (0x1 << 0) #define RMII_RESET_SPEED (0x3 << 14) @@ -57,7 +60,9 @@ struct imx_priv_data { struct clk *clk_tx; struct clk *clk_mem; struct regmap *intf_regmap; + struct regmap *enet_clk_regmap; u32 intf_reg_off; + u32 enet_clk_reg_off; bool rmii_refclk_ext; void __iomem *base_addr; @@ -116,6 +121,18 @@ static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) break; case PHY_INTERFACE_MODE_RMII: val = MX93_GPR_ENET_QOS_INTF_SEL_RMII; + + /* According to NXP AN14149, the direction of the + * TX_CLK must be set to output in RMII mode. + */ + if (dwmac->enet_clk_regmap) + regmap_update_bits(dwmac->enet_clk_regmap, + dwmac->enet_clk_reg_off, + MX93_GPR_ENET_QOS_TX_CLK_SEL_MASK, + MX93_GPR_ENET_QOS_TX_CLK_SEL); + else + dev_warn(dwmac->dev, "TX_CLK can't be set to output mode.\n"); + break; case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: @@ -310,6 +327,16 @@ imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev) dev_err(dev, "Can't get intf mode reg offset (%d)\n", err); return err; } + + dwmac->enet_clk_regmap = syscon_regmap_lookup_by_phandle(np, "enet_clk_sel"); + if (IS_ERR(dwmac->enet_clk_regmap)) + return PTR_ERR(dwmac->enet_clk_regmap); + + err = of_property_read_u32_index(np, "enet_clk_sel", 1, &dwmac->enet_clk_reg_off); + if (err) { + dev_err(dev, "Can't get enet clk sel reg offset (%d)\n", err); + return err; + } } return err;