From patchwork Tue May 28 23:03:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacob Keller X-Patchwork-Id: 13677538 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5704413FD93 for ; Tue, 28 May 2024 23:04:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716937457; cv=none; b=UoneypAY/uqmz5mkWvoCoAPevwfJZFlYSPX++gyQKoFmykQd7PiMH9gTwnsmfgQcfsGERyXf+dXf/7UFy6njAfaAitLz43PCoLmNw1gZNw8N8REUl2tFnXKMbM+9moyayf38veN3aC5Hm29x9SwCMkwJZ2Q49Zuce349OoMUw2U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716937457; c=relaxed/simple; bh=tjIE+ji7hnRs1F4CoS0eYeBauCKCdO/M7j07c/z87FI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=izFWDZmHaH9agAgYIMxF8HE4xOxG2P26038XVjHZNDPou/5qn+AmUhu7RGq2wzA7YofrVWfbAljrXXb1CpuQHZsM4GvNDOAP7NChOGrHFak8aGJbf8u6vjvGtObe1Fswp1RmhmAZUY6WA7sxly/9rMr3+XIPXwcc6sHuzYJ3ToU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mTpTAjGX; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mTpTAjGX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716937457; x=1748473457; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=tjIE+ji7hnRs1F4CoS0eYeBauCKCdO/M7j07c/z87FI=; b=mTpTAjGXIw38pR6QMeI7glQwo6J2tq5/urq+bGjlAG/AAaqY+1Z+Xnp8 nHOiJOICkpRRi5kwdnMsEFQtdnIDF8KYWulOdVHJ6xKb3eTwUeNJOmS39 jTy6Axc3nn/jeK85lrUfNy+190s7+yhaOiLvs7ksLkNeFEblZ2kjnE9r+ qO+fuNP763Dkj3gcCG5Gmh/0iyzZBZFxFg7Y96U5HSENkyZOEEvlK6WY2 RmUCxkGHLQDQR7YhaJKd74Gd81LQgQpfySkXKe+rOd+hpLi0ieTraAtD3 nMN04gZhTUG5PcXyk+kPzakcV1Ral9RNm5dWhlSKenh4PpCbsqn4JeAtq g==; X-CSE-ConnectionGUID: o8dNeBRGR4SEdO/xypP7pA== X-CSE-MsgGUID: jC8jsmnKTZuMJd9mTyQiIQ== X-IronPort-AV: E=McAfee;i="6600,9927,11085"; a="13444892" X-IronPort-AV: E=Sophos;i="6.08,196,1712646000"; d="scan'208";a="13444892" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 May 2024 16:04:12 -0700 X-CSE-ConnectionGUID: jfF6tyneT/CSIUhh+dLhqg== X-CSE-MsgGUID: mUVCBMK1TGagfd1P4bStxQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,196,1712646000"; d="scan'208";a="39672303" Received: from jekeller-desk.amr.corp.intel.com ([10.166.241.1]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 May 2024 16:04:11 -0700 From: Jacob Keller Date: Tue, 28 May 2024 16:03:58 -0700 Subject: [PATCH next 08/11] ice: Change CGU regs struct to anonymous Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240528-next-2024-05-28-ptp-refactors-v1-8-c082739bb6f6@intel.com> References: <20240528-next-2024-05-28-ptp-refactors-v1-0-c082739bb6f6@intel.com> In-Reply-To: <20240528-next-2024-05-28-ptp-refactors-v1-0-c082739bb6f6@intel.com> To: David Miller , Jakub Kicinski , netdev Cc: Jacob Keller , Jiri Pirko , Karol Kolacinski , Przemek Kitszel , Arkadiusz Kubalewski , Pucha Himasekhar Reddy X-Mailer: b4 0.13.0 X-Patchwork-Delegate: kuba@kernel.org From: Karol Kolacinski Simplify the code by using anonymous struct in CGU registers instead of naming each structure 'field'. Suggested-by: Przemek Kitszel Reviewed-by: Przemek Kitszel Reviewed-by: Arkadiusz Kubalewski Signed-off-by: Karol Kolacinski Tested-by: Pucha Himasekhar Reddy Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ice/ice_cgu_regs.h | 12 ++++---- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 44 +++++++++++++-------------- 2 files changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_cgu_regs.h b/drivers/net/ethernet/intel/ice/ice_cgu_regs.h index 57abd52386d0..36aeb10eefb7 100644 --- a/drivers/net/ethernet/intel/ice/ice_cgu_regs.h +++ b/drivers/net/ethernet/intel/ice/ice_cgu_regs.h @@ -23,7 +23,7 @@ union nac_cgu_dword9 { u32 clk_synce0_amp : 2; u32 one_pps_out_amp : 2; u32 misc24 : 12; - } field; + }; u32 val; }; @@ -39,7 +39,7 @@ union nac_cgu_dword19 { u32 japll_ndivratio : 4; u32 japll_iref_ndivratio : 3; u32 misc27 : 1; - } field; + }; u32 val; }; @@ -63,7 +63,7 @@ union nac_cgu_dword22 { u32 fdpllclk_sel_div2 : 1; u32 time1588clk_sel_div2 : 1; u32 misc3 : 1; - } field; + }; u32 val; }; @@ -77,7 +77,7 @@ union nac_cgu_dword24 { u32 ext_synce_sel : 1; u32 ref1588_ck_div : 4; u32 time_ref_sel : 1; - } field; + }; u32 val; }; @@ -92,7 +92,7 @@ union tspll_cntr_bist_settings { u32 i_plllock_cnt_6_0 : 7; u32 i_plllock_cnt_10_7 : 4; u32 reserved200 : 4; - } field; + }; u32 val; }; @@ -109,7 +109,7 @@ union tspll_ro_bwm_lf { u32 afcdone_cri : 1; u32 feedfwrdgain_cal_cri_7_0 : 8; u32 m2fbdivmod_cri_7_0 : 8; - } field; + }; u32 val; }; diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 1b333b1c2738..691ea20811e7 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -393,14 +393,14 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw, /* Log the current clock configuration */ ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", - dw24.field.ts_pll_enable ? "enabled" : "disabled", - ice_clk_src_str(dw24.field.time_ref_sel), - ice_clk_freq_str(dw9.field.time_ref_freq_sel), - bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked"); + dw24.ts_pll_enable ? "enabled" : "disabled", + ice_clk_src_str(dw24.time_ref_sel), + ice_clk_freq_str(dw9.time_ref_freq_sel), + bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked"); /* Disable the PLL before changing the clock source or frequency */ - if (dw24.field.ts_pll_enable) { - dw24.field.ts_pll_enable = 0; + if (dw24.ts_pll_enable) { + dw24.ts_pll_enable = 0; err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); if (err) @@ -408,7 +408,7 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw, } /* Set the frequency */ - dw9.field.time_ref_freq_sel = clk_freq; + dw9.time_ref_freq_sel = clk_freq; err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); if (err) return err; @@ -418,8 +418,8 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw, if (err) return err; - dw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div; - dw19.field.tspll_ndivratio = 1; + dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div; + dw19.tspll_ndivratio = 1; err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val); if (err) @@ -430,8 +430,8 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw, if (err) return err; - dw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div; - dw22.field.time1588clk_sel_div2 = 0; + dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div; + dw22.time1588clk_sel_div2 = 0; err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val); if (err) @@ -442,16 +442,16 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw, if (err) return err; - dw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div; - dw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div; - dw24.field.time_ref_sel = clk_src; + dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div; + dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div; + dw24.time_ref_sel = clk_src; err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); if (err) return err; /* Finally, enable the PLL */ - dw24.field.ts_pll_enable = 1; + dw24.ts_pll_enable = 1; err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); if (err) @@ -464,17 +464,17 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw, if (err) return err; - if (!bwm_lf.field.plllock_true_lock_cri) { + if (!bwm_lf.plllock_true_lock_cri) { dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n"); return -EBUSY; } /* Log the current clock configuration */ ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", - dw24.field.ts_pll_enable ? "enabled" : "disabled", - ice_clk_src_str(dw24.field.time_ref_sel), - ice_clk_freq_str(dw9.field.time_ref_freq_sel), - bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked"); + dw24.ts_pll_enable ? "enabled" : "disabled", + ice_clk_src_str(dw24.time_ref_sel), + ice_clk_freq_str(dw9.time_ref_freq_sel), + bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked"); return 0; } @@ -499,8 +499,8 @@ static int ice_init_cgu_e82x(struct ice_hw *hw) return err; /* Disable sticky lock detection so lock err reported is accurate */ - cntr_bist.field.i_plllock_sel_0 = 0; - cntr_bist.field.i_plllock_sel_1 = 0; + cntr_bist.i_plllock_sel_0 = 0; + cntr_bist.i_plllock_sel_1 = 0; err = ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS, cntr_bist.val);