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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EE30.mail.protection.outlook.com (10.167.242.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7633.15 via Frontend Transport; Fri, 31 May 2024 21:40:26 +0000 Received: from weiserver.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 31 May 2024 16:40:25 -0500 From: Wei Huang To: , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH V2 6/9] PCI/TPH: Retrieve steering tag from ACPI _DSM Date: Fri, 31 May 2024 16:38:38 -0500 Message-ID: <20240531213841.3246055-7-wei.huang2@amd.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240531213841.3246055-1-wei.huang2@amd.com> References: <20240531213841.3246055-1-wei.huang2@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE30:EE_|CH3PR12MB9341:EE_ X-MS-Office365-Filtering-Correlation-Id: 7152c140-1b3e-48fe-7fe1-08dc81ba48e9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|36860700004|7416005|376005|1800799015; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 May 2024 21:40:26.5836 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7152c140-1b3e-48fe-7fe1-08dc81ba48e9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9341 According to PCI SIG ECN, calling the _DSM firmware method for a given CPU_UID returns the steering tags for different types of memory (volatile, non-volatile). These tags are supposed to be used in ST table entry for optimal results. Co-developed-by: Eric Van Tassell Signed-off-by: Eric Van Tassell Signed-off-by: Wei Huang Reviewed-by: Ajit Khaparde Reviewed-by: Somnath Kotur Reviewed-by: Andy Gospodarek --- drivers/pci/pcie/tph.c | 103 +++++++++++++++++++++++++++++++++++++++- include/linux/pci-tph.h | 34 +++++++++++++ 2 files changed, 136 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie/tph.c b/drivers/pci/pcie/tph.c index 320b99c60365..425935a14b62 100644 --- a/drivers/pci/pcie/tph.c +++ b/drivers/pci/pcie/tph.c @@ -158,6 +158,98 @@ static int tph_get_table_location(struct pci_dev *dev, u8 *loc_out) return 0; } +static u16 tph_extract_tag(enum tph_mem_type mem_type, u8 req_type, + union st_info *st_tag) +{ + switch (req_type) { + case PCI_TPH_REQ_TPH_ONLY: /* 8 bit tags */ + switch (mem_type) { + case TPH_MEM_TYPE_VM: + if (st_tag->vm_st_valid) + return st_tag->vm_st; + break; + case TPH_MEM_TYPE_PM: + if (st_tag->pm_st_valid) + return st_tag->pm_st; + break; + } + break; + case PCI_TPH_REQ_EXT_TPH: /* 16 bit tags */ + switch (mem_type) { + case TPH_MEM_TYPE_VM: + if (st_tag->vm_xst_valid) + return st_tag->vm_xst; + break; + case TPH_MEM_TYPE_PM: + if (st_tag->pm_xst_valid) + return st_tag->pm_xst; + break; + } + break; + default: + pr_err("invalid steering tag in ACPI _DSM\n"); + return 0; + } + + return 0; +} + +#define MIN_ST_DSM_REV 7 +#define ST_DSM_FUNC_INDEX 0xf +static bool invoke_dsm(acpi_handle handle, u32 cpu_uid, u8 ph, + u8 target_type, bool cache_ref_valid, + u64 cache_ref, union st_info *st_out) +{ + union acpi_object in_obj, in_buf[3], *out_obj; + + in_buf[0].integer.type = ACPI_TYPE_INTEGER; + in_buf[0].integer.value = 0; /* 0 => processor cache steering tags */ + + in_buf[1].integer.type = ACPI_TYPE_INTEGER; + in_buf[1].integer.value = cpu_uid; + + in_buf[2].integer.type = ACPI_TYPE_INTEGER; + in_buf[2].integer.value = ph & 3; + in_buf[2].integer.value |= (target_type & 1) << 2; + in_buf[2].integer.value |= (cache_ref_valid & 1) << 3; + in_buf[2].integer.value |= (cache_ref << 32); + + in_obj.type = ACPI_TYPE_PACKAGE; + in_obj.package.count = ARRAY_SIZE(in_buf); + in_obj.package.elements = in_buf; + + out_obj = acpi_evaluate_dsm(handle, &pci_acpi_dsm_guid, MIN_ST_DSM_REV, + ST_DSM_FUNC_INDEX, &in_obj); + + if (!out_obj) + return false; + + if (out_obj->type != ACPI_TYPE_BUFFER) { + pr_err("invalid return type %d from TPH _DSM\n", + out_obj->type); + ACPI_FREE(out_obj); + return false; + } + + st_out->value = *((u64 *)(out_obj->buffer.pointer)); + + ACPI_FREE(out_obj); + + return true; +} + +static acpi_handle root_complex_acpi_handle(struct pci_dev *dev) +{ + struct pci_dev *root_port; + + root_port = pcie_find_root_port(dev); + + if (!root_port || !root_port->bus || !root_port->bus->bridge) + return NULL; + + return ACPI_HANDLE(root_port->bus->bridge); +} + static bool msix_nr_in_bounds(struct pci_dev *dev, int msix_nr) { u16 tbl_sz; @@ -441,7 +533,16 @@ bool pcie_tph_get_st(struct pci_dev *dev, unsigned int cpu, enum tph_mem_type mem_type, u8 req_type, u16 *tag) { - *tag = 0; + union st_info info; + + if (!invoke_dsm(root_complex_acpi_handle(dev), cpu, 0, 0, false, 0, + &info)) { + *tag = 0; + return false; + } + + *tag = tph_extract_tag(mem_type, req_type, &info); + pr_debug("%s: cpu=%d tag=%d\n", __func__, cpu, *tag); return true; } diff --git a/include/linux/pci-tph.h b/include/linux/pci-tph.h index 4fbd1e2fd98c..79533c6254c2 100644 --- a/include/linux/pci-tph.h +++ b/include/linux/pci-tph.h @@ -14,6 +14,40 @@ enum tph_mem_type { TPH_MEM_TYPE_PM /* persistent memory type */ }; +/* + * The st_info struct defines the steering tag returned by the firmware _DSM + * method defined in PCI SIG ECN. The specification is available at: + * https://members.pcisig.com/wg/PCI-SIG/document/15470. + + * @vm_st_valid: 8 bit tag for volatile memory is valid + * @vm_xst_valid: 16 bit tag for volatile memory is valid + * @vm_ignore: 1 => was and will be ignored, 0 => ph should be supplied + * @vm_st: 8 bit steering tag for volatile mem + * @vm_xst: 16 bit steering tag for volatile mem + * @pm_st_valid: 8 bit tag for persistent memory is valid + * @pm_xst_valid: 16 bit tag for persistent memory is valid + * @pm_ignore: 1 => was and will be ignore, 0 => ph should be supplied + * @pm_st: 8 bit steering tag for persistent mem + * @pm_xst: 16 bit steering tag for persistent mem + */ +union st_info { + struct { + u64 vm_st_valid:1, + vm_xst_valid:1, + vm_ph_ignore:1, + rsvd1:5, + vm_st:8, + vm_xst:16, + pm_st_valid:1, + pm_xst_valid:1, + pm_ph_ignore:1, + rsvd2:5, + pm_st:8, + pm_xst:16; + }; + u64 value; +}; + #ifdef CONFIG_PCIE_TPH int pcie_tph_disable(struct pci_dev *dev); int tph_set_dev_nostmode(struct pci_dev *dev);