@@ -222,15 +222,11 @@ static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat)
return -EINVAL;
}
-static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
+static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
{
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
u32 reg = dwmac->mode_reg;
- int val, ret;
-
- ret = stm32mp1_select_ethck_external(plat_dat);
- if (ret)
- return ret;
+ int val;
switch (plat_dat->mac_interface) {
case PHY_INTERFACE_MODE_MII:
@@ -265,10 +261,6 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
return -EINVAL;
}
- ret = stm32mp1_validate_ethck_rate(plat_dat);
- if (ret)
- return ret;
-
/* Need to update PMCCLRR (clear register) */
regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
dwmac->ops->syscfg_eth_mask);
@@ -278,6 +270,21 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
dwmac->ops->syscfg_eth_mask, val);
}
+static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
+{
+ int ret;
+
+ ret = stm32mp1_select_ethck_external(plat_dat);
+ if (ret)
+ return ret;
+
+ ret = stm32mp1_validate_ethck_rate(plat_dat);
+ if (ret)
+ return ret;
+
+ return stm32mp1_configure_pmcr(plat_dat);
+}
+
static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
{
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;